mirror of https://github.com/YosysHQ/yosys.git
29bd81d662
Without unbuffering output wires of, at least, toplevel modules, it is not possible to have most designs that rely on IO via toplevel ports (as opposed to using exclusively blackboxes) converge within one delta cycle. That seriously impairs the performance of CXXRTL. This commit avoids unbuffering outputs of all modules solely so that in future, CXXRTL could gain fully separate compilation, and not for any present technical reason. |
||
---|---|---|
.. | ||
Makefile.inc | ||
cxxrtl.h | ||
cxxrtl_backend.cc | ||
cxxrtl_capi.cc | ||
cxxrtl_capi.h | ||
cxxrtl_vcd.h | ||
cxxrtl_vcd_capi.cc | ||
cxxrtl_vcd_capi.h |