yosys/backends/cxxrtl
whitequark 29bd81d662 cxxrtl: unbuffer output wires of toplevel module.
Without unbuffering output wires of, at least, toplevel modules, it
is not possible to have most designs that rely on IO via toplevel
ports (as opposed to using exclusively blackboxes) converge within
one delta cycle. That seriously impairs the performance of CXXRTL.

This commit avoids unbuffering outputs of all modules solely so that
in future, CXXRTL could gain fully separate compilation, and not for
any present technical reason.
2020-06-12 00:31:57 +00:00
..
Makefile.inc cxxrtl: rename cxxrtl.cc→cxxrtl_backend.cc. 2020-06-07 03:48:40 +00:00
cxxrtl.h Merge pull request #2141 from whitequark/cxxrtl-cxx11 2020-06-10 17:10:15 +00:00
cxxrtl_backend.cc cxxrtl: unbuffer output wires of toplevel module. 2020-06-12 00:31:57 +00:00
cxxrtl_capi.cc cxxrtl: add a C API for writing VCD dumps. 2020-06-07 03:48:00 +00:00
cxxrtl_capi.h cxxrtl: disambiguate values/wires and their aliases in debug info. 2020-06-10 14:39:45 +00:00
cxxrtl_vcd.h cxxrtl: disambiguate values/wires and their aliases in debug info. 2020-06-10 14:39:45 +00:00
cxxrtl_vcd_capi.cc cxxrtl: add missing namespace. 2020-06-09 06:26:43 +00:00
cxxrtl_vcd_capi.h Fix formatting. NFC. 2020-06-10 15:48:40 +00:00