Claire Xenia Wolf 46f0932c4c Ignore empty parameters in Verilog module instantiations ... Fixes #2394 Signed-off-by: Claire Xenia Wolf <claire@symbioticeda.com>		2020-10-01 18:27:16 +02:00
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.gitignore	Add "make coverage"	2018-08-27 14:22:21 +02:00
Makefile.inc	Treat all bison warnings as errors in verilog front-end	2020-07-15 11:57:31 +02:00
const2ast.cc	Replacing log_error for log_file_error due consistency	2020-03-31 12:01:29 -06:00
preproc.cc	MSVC does not understand __builtin_unreachable	2020-06-17 15:10:08 +02:00
preproc.h	Add support for SystemVerilog-style `define to Verilog frontend	2020-03-27 16:08:26 +00:00
verilog_frontend.cc	Use C++11 final/override keywords.	2020-06-18 23:34:52 +00:00
verilog_frontend.h	frontend: cleanup to use more ID::*, more dict<> instead of map<>	2020-05-04 10:48:37 -07:00
verilog_lexer.l	Merge pull request #2179 from splhack/static-cast	2020-07-01 16:40:20 +02:00
verilog_parser.y	Ignore empty parameters in Verilog module instantiations	2020-10-01 18:27:16 +02:00