mirror of https://github.com/YosysHQ/yosys.git
756 lines
24 KiB
C++
756 lines
24 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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// [[CITE]] Temporal Induction by Incremental SAT Solving
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// Niklas Een and Niklas Sörensson (2003)
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// http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.4.8161
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/consteval.h"
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#include "kernel/sigtools.h"
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#include "kernel/log.h"
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#include "kernel/satgen.h"
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#include <stdlib.h>
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#include <stdio.h>
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#include <algorithm>
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namespace {
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struct SatHelper
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{
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RTLIL::Design *design;
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RTLIL::Module *module;
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ezDefaultSAT ez;
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SigMap sigmap;
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CellTypes ct;
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SatGen satgen;
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// additional constraints
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std::vector<std::pair<std::string, std::string>> sets, prove;
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std::map<int, std::vector<std::pair<std::string, std::string>>> sets_at;
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std::map<int, std::vector<std::string>> unsets_at;
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// model variables
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std::vector<std::string> shows;
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SigPool show_signal_pool;
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SigSet<RTLIL::Cell*> show_drivers;
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int max_timestep, timeout;
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bool gotTimeout;
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SatHelper(RTLIL::Design *design, RTLIL::Module *module) :
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design(design), module(module), sigmap(module), ct(design), satgen(&ez, design, &sigmap)
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{
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max_timestep = -1;
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timeout = 0;
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gotTimeout = false;
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}
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void setup(int timestep = -1)
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{
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if (timestep > 0)
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log ("\nSetting up time step %d:\n", timestep);
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else
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log ("\nSetting up SAT problem:\n");
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if (timestep > max_timestep)
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max_timestep = timestep;
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RTLIL::SigSpec big_lhs, big_rhs;
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for (auto &s : sets)
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{
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RTLIL::SigSpec lhs, rhs;
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if (!RTLIL::SigSpec::parse(lhs, module, s.first))
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log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.first.c_str());
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if (!RTLIL::SigSpec::parse(rhs, module, s.second))
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log_cmd_error("Failed to parse rhs set expression `%s'.\n", s.second.c_str());
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show_signal_pool.add(sigmap(lhs));
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show_signal_pool.add(sigmap(rhs));
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if (lhs.width != rhs.width)
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log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n",
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s.first.c_str(), log_signal(lhs), lhs.width, s.second.c_str(), log_signal(rhs), rhs.width);
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log("Import set-constraint: %s = %s\n", log_signal(lhs), log_signal(rhs));
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big_lhs.remove2(lhs, &big_rhs);
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big_lhs.append(lhs);
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big_rhs.append(rhs);
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}
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for (auto &s : sets_at[timestep])
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{
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RTLIL::SigSpec lhs, rhs;
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if (!RTLIL::SigSpec::parse(lhs, module, s.first))
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log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.first.c_str());
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if (!RTLIL::SigSpec::parse(rhs, module, s.second))
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log_cmd_error("Failed to parse rhs set expression `%s'.\n", s.second.c_str());
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show_signal_pool.add(sigmap(lhs));
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show_signal_pool.add(sigmap(rhs));
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if (lhs.width != rhs.width)
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log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n",
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s.first.c_str(), log_signal(lhs), lhs.width, s.second.c_str(), log_signal(rhs), rhs.width);
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log("Import set-constraint for timestep: %s = %s\n", log_signal(lhs), log_signal(rhs));
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big_lhs.remove2(lhs, &big_rhs);
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big_lhs.append(lhs);
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big_rhs.append(rhs);
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}
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for (auto &s : unsets_at[timestep])
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{
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RTLIL::SigSpec lhs;
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if (!RTLIL::SigSpec::parse(lhs, module, s))
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log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.c_str());
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show_signal_pool.add(sigmap(lhs));
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log("Import unset-constraint for timestep: %s\n", log_signal(lhs));
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big_lhs.remove2(lhs, &big_rhs);
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}
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log("Final constraint equation: %s = %s\n", log_signal(big_lhs), log_signal(big_rhs));
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std::vector<int> lhs_vec = satgen.importSigSpec(big_lhs, timestep);
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std::vector<int> rhs_vec = satgen.importSigSpec(big_rhs, timestep);
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ez.assume(ez.vec_eq(lhs_vec, rhs_vec));
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int import_cell_counter = 0;
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for (auto &c : module->cells)
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if (design->selected(module, c.second)) {
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// log("Import cell: %s\n", RTLIL::id2cstr(c.first));
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if (satgen.importCell(c.second, timestep)) {
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for (auto &p : c.second->connections)
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if (ct.cell_output(c.second->type, p.first))
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show_drivers.insert(sigmap(p.second), c.second);
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import_cell_counter++;
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} else
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log("Warning: failed to import cell %s (type %s) to SAT database.\n", RTLIL::id2cstr(c.first), RTLIL::id2cstr(c.second->type));
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}
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log("Imported %d cells to SAT database.\n", import_cell_counter);
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}
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int setup_proof(int timestep = -1)
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{
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assert(prove.size() > 0);
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RTLIL::SigSpec big_lhs, big_rhs;
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for (auto &s : prove)
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{
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RTLIL::SigSpec lhs, rhs;
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if (!RTLIL::SigSpec::parse(lhs, module, s.first))
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log_cmd_error("Failed to parse lhs proof expression `%s'.\n", s.first.c_str());
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if (!RTLIL::SigSpec::parse(rhs, module, s.second))
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log_cmd_error("Failed to parse rhs proof expression `%s'.\n", s.second.c_str());
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show_signal_pool.add(sigmap(lhs));
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show_signal_pool.add(sigmap(rhs));
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if (lhs.width != rhs.width)
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log_cmd_error("Proof expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n",
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s.first.c_str(), log_signal(lhs), lhs.width, s.second.c_str(), log_signal(rhs), rhs.width);
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log("Import proof-constraint: %s = %s\n", log_signal(lhs), log_signal(rhs));
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big_lhs.remove2(lhs, &big_rhs);
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big_lhs.append(lhs);
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big_rhs.append(rhs);
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}
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log("Final proof equation: %s = %s\n", log_signal(big_lhs), log_signal(big_rhs));
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std::vector<int> lhs_vec = satgen.importSigSpec(big_lhs, timestep);
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std::vector<int> rhs_vec = satgen.importSigSpec(big_rhs, timestep);
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return ez.vec_eq(lhs_vec, rhs_vec);
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}
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void force_unique_state(int timestep_from, int timestep_to)
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{
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RTLIL::SigSpec state_signals = satgen.initial_state.export_all();
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for (int i = timestep_from; i < timestep_to; i++)
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ez.assume(ez.vec_ne(satgen.importSigSpec(state_signals, i), satgen.importSigSpec(state_signals, timestep_to)));
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}
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bool solve(const std::vector<int> &assumptions)
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{
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log_assert(gotTimeout == false);
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ez.setSolverTimeout(timeout);
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bool success = ez.solve(modelExpressions, modelValues, assumptions);
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if (ez.getSolverTimoutStatus())
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gotTimeout = true;
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return success;
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}
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bool solve(int a = 0, int b = 0, int c = 0, int d = 0, int e = 0, int f = 0)
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{
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log_assert(gotTimeout == false);
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ez.setSolverTimeout(timeout);
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bool success = ez.solve(modelExpressions, modelValues, a, b, c, d, e, f);
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if (ez.getSolverTimoutStatus())
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gotTimeout = true;
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return success;
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}
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struct ModelBlockInfo {
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int timestep, offset, width;
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std::string description;
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bool operator < (const ModelBlockInfo &other) const {
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if (timestep != other.timestep)
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return timestep < other.timestep;
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if (description != other.description)
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return description < other.description;
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if (offset != other.offset)
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return offset < other.offset;
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if (width != other.width)
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return width < other.width;
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return false;
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}
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};
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std::vector<int> modelExpressions;
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std::vector<bool> modelValues;
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std::set<ModelBlockInfo> modelInfo;
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void generate_model()
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{
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RTLIL::SigSpec modelSig;
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modelExpressions.clear();
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modelInfo.clear();
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// Add "show" signals or alternatively the leaves on the input cone on all set and prove signals
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if (shows.size() == 0)
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{
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SigPool queued_signals, handled_signals, final_signals;
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queued_signals = show_signal_pool;
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while (queued_signals.size() > 0) {
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RTLIL::SigSpec sig = queued_signals.export_one();
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queued_signals.del(sig);
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handled_signals.add(sig);
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std::set<RTLIL::Cell*> drivers = show_drivers.find(sig);
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if (drivers.size() == 0) {
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final_signals.add(sig);
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} else {
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for (auto &d : drivers)
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for (auto &p : d->connections) {
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if (d->type == "$dff" && p.first == "\\CLK")
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continue;
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if (d->type.substr(0, 6) == "$_DFF_" && p.first == "\\C")
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continue;
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queued_signals.add(handled_signals.remove(sigmap(p.second)));
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}
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}
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}
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modelSig = final_signals.export_all();
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// additionally add all set and prove signals directly
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// (it improves user confidence if we write the constraints back ;-)
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modelSig.append(show_signal_pool.export_all());
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}
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else
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{
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for (auto &s : shows) {
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RTLIL::SigSpec sig;
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if (!RTLIL::SigSpec::parse(sig, module, s))
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log_cmd_error("Failed to parse show expression `%s'.\n", s.c_str());
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log("Import show expression: %s\n", log_signal(sig));
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modelSig.append(sig);
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}
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}
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modelSig.sort_and_unify();
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// log("Model signals: %s\n", log_signal(modelSig));
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for (auto &c : modelSig.chunks)
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if (c.wire != NULL) {
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ModelBlockInfo info;
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RTLIL::SigSpec chunksig = c;
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info.width = chunksig.width;
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info.description = log_signal(chunksig);
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for (int timestep = -1; timestep <= max_timestep; timestep++) {
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if ((timestep == -1 && max_timestep > 0) || timestep == 0)
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continue;
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std::vector<int> vec = satgen.importSigSpec(chunksig, timestep);
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info.timestep = timestep;
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info.offset = modelExpressions.size();
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modelExpressions.insert(modelExpressions.end(), vec.begin(), vec.end());
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modelInfo.insert(info);
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}
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}
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// Add zero step signals as collected by satgen
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modelSig = satgen.initial_state.export_all();
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for (auto &c : modelSig.chunks)
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if (c.wire != NULL) {
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ModelBlockInfo info;
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RTLIL::SigSpec chunksig = c;
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info.timestep = 0;
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info.offset = modelExpressions.size();
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info.width = chunksig.width;
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info.description = log_signal(chunksig);
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std::vector<int> vec = satgen.importSigSpec(chunksig, 1);
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modelExpressions.insert(modelExpressions.end(), vec.begin(), vec.end());
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modelInfo.insert(info);
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}
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}
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void print_model()
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{
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int maxModelName = 10;
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int maxModelWidth = 10;
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for (auto &info : modelInfo) {
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maxModelName = std::max(maxModelName, int(info.description.size()));
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maxModelWidth = std::max(maxModelWidth, info.width);
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}
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log("\n");
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int last_timestep = -2;
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for (auto &info : modelInfo)
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{
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RTLIL::Const value;
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for (int i = 0; i < info.width; i++) {
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value.bits.push_back(modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0);
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if (modelValues.size() == 2*modelExpressions.size() && modelValues.at(modelExpressions.size()+info.offset+i))
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value.bits.back() = RTLIL::State::Sx;
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}
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if (info.timestep != last_timestep) {
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const char *hline = "---------------------------------------------------------------------------------------------------"
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"---------------------------------------------------------------------------------------------------"
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"---------------------------------------------------------------------------------------------------";
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if (last_timestep == -2) {
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log(max_timestep > 0 ? " Time " : " ");
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log("%-*s %10s %10s %*s\n", maxModelName+10, "Signal Name", "Dec", "Hex", maxModelWidth+5, "Bin");
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}
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log(max_timestep > 0 ? " ---- " : " ");
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log("%*.*s %10.10s %10.10s %*.*s\n", maxModelName+10, maxModelName+10,
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hline, hline, hline, maxModelWidth+5, maxModelWidth+5, hline);
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last_timestep = info.timestep;
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}
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if (max_timestep > 0) {
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if (info.timestep > 0)
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log(" %4d ", info.timestep);
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else
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log(" init ");
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} else
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log(" ");
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if (info.width <= 32)
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log("%-*s %10d %10x %*s\n", maxModelName+10, info.description.c_str(), value.as_int(), value.as_int(), maxModelWidth+5, value.as_string().c_str());
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else
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log("%-*s %10s %10s %*s\n", maxModelName+10, info.description.c_str(), "--", "--", maxModelWidth+5, value.as_string().c_str());
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}
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if (last_timestep == -2)
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log(" no model variables selected for display.\n");
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}
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void invalidate_model()
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{
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std::vector<int> clause;
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for (size_t i = 0; i < modelExpressions.size(); i++)
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clause.push_back(modelValues.at(i) ? ez.NOT(modelExpressions.at(i)) : modelExpressions.at(i));
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ez.assume(ez.expression(ezSAT::OpOr, clause));
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}
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};
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} /* namespace */
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static void print_proof_failed()
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{
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log("\n");
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log(" ______ ___ ___ _ _ _ _ \n");
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log(" (_____ \\ / __) / __) (_) | | | |\n");
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log(" _____) )___ ___ ___ _| |__ _| |__ _____ _| | _____ __| | |\n");
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log(" | ____/ ___) _ \\ / _ (_ __) (_ __|____ | | || ___ |/ _ |_|\n");
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log(" | | | | | |_| | |_| || | | | / ___ | | || ____( (_| |_ \n");
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log(" |_| |_| \\___/ \\___/ |_| |_| \\_____|_|\\_)_____)\\____|_|\n");
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log("\n");
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}
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static void print_timeout()
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{
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log("\n");
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log(" _____ _ _ _____ ____ _ _____\n");
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log(" /__ __\\/ \\/ \\__/|/ __// _ \\/ \\ /\\/__ __\\\n");
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log(" / \\ | || |\\/||| \\ | / \\|| | || / \\\n");
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log(" | | | || | ||| /_ | \\_/|| \\_/| | |\n");
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log(" \\_/ \\_/\\_/ \\|\\____\\\\____/\\____/ \\_/\n");
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log("\n");
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}
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static void print_qed()
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{
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log("\n");
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log(" /$$$$$$ /$$$$$$$$ /$$$$$$$ \n");
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log(" /$$__ $$ | $$_____/ | $$__ $$ \n");
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log(" | $$ \\ $$ | $$ | $$ \\ $$ \n");
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log(" | $$ | $$ | $$$$$ | $$ | $$ \n");
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log(" | $$ | $$ | $$__/ | $$ | $$ \n");
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log(" | $$/$$ $$ | $$ | $$ | $$ \n");
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log(" | $$$$$$/ /$$| $$$$$$$$ /$$| $$$$$$$//$$\n");
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log(" \\____ $$$|__/|________/|__/|_______/|__/\n");
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log(" \\__/ \n");
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log("\n");
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}
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struct SatPass : public Pass {
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SatPass() : Pass("sat", "solve a SAT problem in the circuit") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" sat [options] [selection]\n");
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log("\n");
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log("This command solves a SAT problem defined over the currently selected circuit\n");
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log("and additional constraints passed as parameters.\n");
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log("\n");
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log(" -all\n");
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log(" show all solutions to the problem (this can grow exponentially, use\n");
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log(" -max <N> instead to get <N> solutions)\n");
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log("\n");
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log(" -max <N>\n");
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log(" like -all, but limit number of solutions to <N>\n");
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log("\n");
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log(" -set <signal> <value>\n");
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log(" set the specified signal to the specified value.\n");
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log("\n");
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log(" -show <signal>\n");
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log(" show the model for the specified signal. if no -show option is\n");
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log(" passed then a set of signals to be shown is automatically selected.\n");
|
|
log("\n");
|
|
log(" -ignore_div_by_zero\n");
|
|
log(" ignore all solutions that involve a division by zero\n");
|
|
log("\n");
|
|
log("The following options can be used to set up a sequential problem:\n");
|
|
log("\n");
|
|
log(" -seq <N>\n");
|
|
log(" set up a sequential problem with <N> time steps. The steps will\n");
|
|
log(" be numbered from 1 to N.\n");
|
|
log("\n");
|
|
log(" -set-at <N> <signal> <value>\n");
|
|
log(" -unset-at <N> <signal>\n");
|
|
log(" set or unset the specified signal to the specified value in the\n");
|
|
log(" given timestep. this has priority over a -set for the same signal.\n");
|
|
log("\n");
|
|
log("The following additional options can be used to set up a proof. If also -seq\n");
|
|
log("is passed, a temporal induction proof is performed.\n");
|
|
log("\n");
|
|
log(" -prove <signal> <value>\n");
|
|
log(" Attempt to proof that <signal> is always <value>. In a temporal\n");
|
|
log(" induction proof it is proven that the condition holds forever after\n");
|
|
log(" the number of time steps passed using -seq.\n");
|
|
log("\n");
|
|
log(" -maxsteps <N>\n");
|
|
log(" Set a maximum length for the induction.\n");
|
|
log("\n");
|
|
log(" -timeout <N>\n");
|
|
log(" Maximum number of seconds a single SAT instance may take.\n");
|
|
log("\n");
|
|
log(" -verify\n");
|
|
log(" Return an error and stop the synthesis script if the proof fails.\n");
|
|
log("\n");
|
|
log(" -verify-no-timeout\n");
|
|
log(" Like -verify but do not return an error for timeouts.\n");
|
|
log("\n");
|
|
}
|
|
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
|
|
{
|
|
std::vector<std::pair<std::string, std::string>> sets, prove;
|
|
std::map<int, std::vector<std::pair<std::string, std::string>>> sets_at;
|
|
std::map<int, std::vector<std::string>> unsets_at;
|
|
std::vector<std::string> shows;
|
|
int loopcount = 0, seq_len = 0, maxsteps = 0, timeout = 0;
|
|
bool verify = false, fail_on_timeout = false, ignore_div_by_zero = false;
|
|
|
|
log_header("Executing SAT pass (solving SAT problems in the circuit).\n");
|
|
|
|
size_t argidx;
|
|
for (argidx = 1; argidx < args.size(); argidx++) {
|
|
if (args[argidx] == "-all") {
|
|
loopcount = -1;
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-verify") {
|
|
fail_on_timeout = true;
|
|
verify = true;
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-verify-no-timeout") {
|
|
verify = true;
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-timeout" && argidx+1 < args.size()) {
|
|
timeout = atoi(args[++argidx].c_str());
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-max" && argidx+1 < args.size()) {
|
|
loopcount = atoi(args[++argidx].c_str());
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-maxsteps" && argidx+1 < args.size()) {
|
|
maxsteps = atoi(args[++argidx].c_str());
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-ignore_div_by_zero" && argidx+1 < args.size()) {
|
|
ignore_div_by_zero = true;
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-set" && argidx+2 < args.size()) {
|
|
std::string lhs = args[++argidx].c_str();
|
|
std::string rhs = args[++argidx].c_str();
|
|
sets.push_back(std::pair<std::string, std::string>(lhs, rhs));
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-prove" && argidx+2 < args.size()) {
|
|
std::string lhs = args[++argidx].c_str();
|
|
std::string rhs = args[++argidx].c_str();
|
|
prove.push_back(std::pair<std::string, std::string>(lhs, rhs));
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-seq" && argidx+1 < args.size()) {
|
|
seq_len = atoi(args[++argidx].c_str());
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-set-at" && argidx+3 < args.size()) {
|
|
int timestep = atoi(args[++argidx].c_str());
|
|
std::string lhs = args[++argidx].c_str();
|
|
std::string rhs = args[++argidx].c_str();
|
|
sets_at[timestep].push_back(std::pair<std::string, std::string>(lhs, rhs));
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-unset-at" && argidx+2 < args.size()) {
|
|
int timestep = atoi(args[++argidx].c_str());
|
|
std::string lhs = args[++argidx].c_str();
|
|
unsets_at[timestep].push_back(lhs);
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-show" && argidx+1 < args.size()) {
|
|
shows.push_back(args[++argidx]);
|
|
continue;
|
|
}
|
|
break;
|
|
}
|
|
extra_args(args, argidx, design);
|
|
|
|
RTLIL::Module *module = NULL;
|
|
for (auto &mod_it : design->modules)
|
|
if (design->selected(mod_it.second)) {
|
|
if (module)
|
|
log_cmd_error("Only one module must be selected for the SAT pass! (selected: %s and %s)\n",
|
|
RTLIL::id2cstr(module->name), RTLIL::id2cstr(mod_it.first));
|
|
module = mod_it.second;
|
|
}
|
|
if (module == NULL)
|
|
log_cmd_error("Can't perform SAT on an empty selection!\n");
|
|
|
|
if (prove.size() == 0 && verify)
|
|
log_cmd_error("Got -verify but nothing to prove!\n");
|
|
|
|
if (prove.size() > 0 && seq_len > 0)
|
|
{
|
|
if (loopcount > 0)
|
|
log_cmd_error("The options -max and -all are not supported for temporal induction proofs!\n");
|
|
|
|
SatHelper basecase(design, module);
|
|
SatHelper inductstep(design, module);
|
|
|
|
basecase.sets = sets;
|
|
basecase.prove = prove;
|
|
basecase.sets_at = sets_at;
|
|
basecase.unsets_at = unsets_at;
|
|
basecase.shows = shows;
|
|
basecase.timeout = timeout;
|
|
basecase.satgen.ignore_div_by_zero = ignore_div_by_zero;
|
|
|
|
for (int timestep = 1; timestep <= seq_len; timestep++)
|
|
basecase.setup(timestep);
|
|
|
|
inductstep.sets = sets;
|
|
inductstep.prove = prove;
|
|
inductstep.shows = shows;
|
|
inductstep.timeout = timeout;
|
|
inductstep.satgen.ignore_div_by_zero = ignore_div_by_zero;
|
|
|
|
inductstep.setup(1);
|
|
inductstep.ez.assume(inductstep.setup_proof(1));
|
|
|
|
for (int inductlen = 1; inductlen <= maxsteps || maxsteps == 0; inductlen++)
|
|
{
|
|
log("\n** Trying induction with length %d **\n", inductlen);
|
|
|
|
// phase 1: proving base case
|
|
|
|
basecase.setup(seq_len + inductlen);
|
|
int property = basecase.setup_proof(seq_len + inductlen);
|
|
basecase.generate_model();
|
|
|
|
if (inductlen > 1)
|
|
basecase.force_unique_state(seq_len + 1, seq_len + inductlen);
|
|
|
|
log("\n[base case] Solving problem with %d variables and %d clauses..\n",
|
|
basecase.ez.numCnfVariables(), basecase.ez.numCnfClauses());
|
|
|
|
if (basecase.solve(basecase.ez.NOT(property))) {
|
|
log("SAT temporal induction proof finished - model found for base case: FAIL!\n");
|
|
print_proof_failed();
|
|
basecase.print_model();
|
|
goto tip_failed;
|
|
}
|
|
|
|
if (basecase.gotTimeout)
|
|
goto timeout;
|
|
|
|
log("Base case for induction length %d proven.\n", inductlen);
|
|
basecase.ez.assume(property);
|
|
|
|
// phase 2: proving induction step
|
|
|
|
inductstep.setup(inductlen + 1);
|
|
property = inductstep.setup_proof(inductlen + 1);
|
|
inductstep.generate_model();
|
|
|
|
if (inductlen > 1)
|
|
inductstep.force_unique_state(1, inductlen + 1);
|
|
|
|
log("\n[induction step] Solving problem with %d variables and %d clauses..\n",
|
|
inductstep.ez.numCnfVariables(), inductstep.ez.numCnfClauses());
|
|
|
|
if (!inductstep.solve(inductstep.ez.NOT(property))) {
|
|
if (inductstep.gotTimeout)
|
|
goto timeout;
|
|
log("Induction step proven: SUCCESS!\n");
|
|
print_qed();
|
|
goto tip_success;
|
|
}
|
|
|
|
log("Induction step failed. Incrementing induction length.\n");
|
|
inductstep.ez.assume(property);
|
|
|
|
inductstep.print_model();
|
|
}
|
|
|
|
log("\nReached maximum number of time steps -> proof failed.\n");
|
|
print_proof_failed();
|
|
|
|
tip_failed:
|
|
if (verify) {
|
|
log("\n");
|
|
log_error("Called with -verify and proof did fail!\n");
|
|
}
|
|
|
|
tip_success:;
|
|
}
|
|
else
|
|
{
|
|
if (maxsteps > 0)
|
|
log_cmd_error("The options -maxsteps is only supported for temporal induction proofs!\n");
|
|
|
|
SatHelper sathelper(design, module);
|
|
sathelper.sets = sets;
|
|
sathelper.prove = prove;
|
|
sathelper.sets_at = sets_at;
|
|
sathelper.unsets_at = unsets_at;
|
|
sathelper.shows = shows;
|
|
sathelper.timeout = timeout;
|
|
sathelper.satgen.ignore_div_by_zero = ignore_div_by_zero;
|
|
|
|
if (seq_len == 0) {
|
|
sathelper.setup();
|
|
if (sathelper.prove.size() > 0)
|
|
sathelper.ez.assume(sathelper.ez.NOT(sathelper.setup_proof()));
|
|
} else {
|
|
for (int timestep = 1; timestep <= seq_len; timestep++)
|
|
sathelper.setup(timestep);
|
|
}
|
|
sathelper.generate_model();
|
|
|
|
#if 0
|
|
// print CNF for debugging
|
|
sathelper.ez.printDIMACS(stdout, true);
|
|
#endif
|
|
|
|
bool did_rerun = false;
|
|
|
|
rerun_solver:
|
|
log("\nSolving problem with %d variables and %d clauses..\n",
|
|
sathelper.ez.numCnfVariables(), sathelper.ez.numCnfClauses());
|
|
|
|
if (sathelper.solve())
|
|
{
|
|
if (prove.size() == 0) {
|
|
log("SAT solving finished - model found:\n");
|
|
} else {
|
|
log("SAT proof finished - model found: FAIL!\n");
|
|
print_proof_failed();
|
|
}
|
|
|
|
sathelper.print_model();
|
|
|
|
if (loopcount != 0) {
|
|
loopcount--, did_rerun = true;
|
|
sathelper.invalidate_model();
|
|
goto rerun_solver;
|
|
}
|
|
|
|
if (verify) {
|
|
log("\n");
|
|
log_error("Called with -verify and proof did fail!\n");
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (sathelper.gotTimeout)
|
|
goto timeout;
|
|
if (did_rerun)
|
|
log("SAT solving finished - no more models found.\n");
|
|
else if (prove.size() == 0)
|
|
log("SAT solving finished - no model found.\n");
|
|
else {
|
|
log("SAT proof finished - no model found: SUCCESS!\n");
|
|
print_qed();
|
|
}
|
|
}
|
|
|
|
if (verify && did_rerun) {
|
|
log("\n");
|
|
log_error("Called with -verify and proof did fail!\n");
|
|
}
|
|
}
|
|
|
|
if (0) {
|
|
timeout:
|
|
log("Interrupted SAT solver: TIMEOUT!\n");
|
|
print_timeout();
|
|
if (fail_on_timeout)
|
|
log_error("Called with -verify and proof did time out!\n");
|
|
}
|
|
}
|
|
} SatPass;
|
|
|