mirror of https://github.com/YosysHQ/yosys.git
44 lines
1.2 KiB
Plaintext
44 lines
1.2 KiB
Plaintext
# NB: Inputs/Outputs must be ordered alphabetically
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# (with exceptions for carry in/out)
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# Box 1 : CCU2C (2xCARRY + 2xLUT4)
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# Outputs: S0, S1, COUT
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# (NB: carry chain input/output must be last
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# input/output and bus has been moved
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# there overriding the otherwise
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# alphabetical ordering)
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# name ID w/b ins outs
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CCU2C 1 1 9 3
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#A0 A1 B0 B1 C0 C1 D0 D1 CIN
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379 - 379 - 275 - 141 - 257
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630 379 630 379 526 275 392 141 273
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516 516 516 516 412 412 278 278 43
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# Box 2 : TRELLIS_DPR16X4_COMB (16x4 dist ram)
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# Outputs: DO0, DO1, DO2, DO3
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# name ID w/b ins outs
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$__ABC_DPR16X4_COMB 2 0 8 4
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#A0 A1 A2 A3 RAD0 RAD1 RAD2 RAD3
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0 0 0 0 141 379 275 379
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0 0 0 0 141 379 275 379
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0 0 0 0 141 379 275 379
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0 0 0 0 141 379 275 379
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# Box 3 : PFUMX (MUX2)
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# Outputs: Z
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# name ID w/b ins outs
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PFUMX 3 1 3 1
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#ALUT BLUT C0
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98 98 151
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# Box 4 : L6MUX21 (MUX2)
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# Outputs: Z
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# name ID w/b ins outs
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L6MUX21 4 1 3 1
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#D0 D1 SD
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140 141 148
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