yosys/frontends/verilog
Jannis Harder fb1c2be76b verilog: Support void functions
The difference between void functions and tasks is that always_comb's
implicit sensitivity list behaves as if functions were inlined, but
ignores signals read only in tasks. This only matters for event based
simulation, and for synthesis we can treat a void function like a task.
2023-03-20 12:52:46 +01:00
..
.gitignore Add "make coverage" 2018-08-27 14:22:21 +02:00
Makefile.inc Treat all bison warnings as errors in verilog front-end 2020-07-15 11:57:31 +02:00
const2ast.cc Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
preproc.cc set default_nettype to wire for resetall 2022-08-10 13:28:19 +02:00
preproc.h verilog: save and restore overwritten macro arguments 2021-07-28 21:52:16 -04:00
verilog_frontend.cc verilog: Squash a memory leak. 2021-06-14 17:07:41 +02:00
verilog_frontend.h verilog: Squash a memory leak. 2021-06-14 17:07:41 +02:00
verilog_lexer.l verilog: Support void functions 2023-03-20 12:52:46 +01:00
verilog_parser.y verilog: Support void functions 2023-03-20 12:52:46 +01:00