yosys/techlibs
Diego H 266993408a Refactoring memory attribute matching based on IEEE 1364.1 and Tool specific 2019-12-13 15:43:24 -06:00
..
achronix Revert "synth_* with -retime option now calls abc with -D 1 as well" 2019-04-18 07:59:16 -07:00
anlogic make note that it is for latch mode 2019-09-18 17:48:16 +02:00
common Do not map $eq and $ne in cmp2lut, only proper arithmetic cmp 2019-11-11 15:07:29 +01:00
coolrunner2 coolrunner2: remove spurious log_pop() call, fixes #1463 2019-11-23 06:21:40 +01:00
easic Revert "synth_* with -retime option now calls abc with -D 1 as well" 2019-04-18 07:59:16 -07:00
ecp5 Fix bitwidth mismatch; suppresses iverilog warning 2019-12-11 13:02:07 -08:00
efinix FF should be initialized to 0 2019-10-04 13:27:10 +02:00
gowin Use -match-init to not synth contradicting init values 2019-12-03 15:12:25 +01:00
greenpak4 Revert "synth_* with -retime option now calls abc with -D 1 as well" 2019-04-18 07:59:16 -07:00
ice40 ice40_opt to restore attributes/name when unwrapping 2019-12-09 14:29:29 -08:00
intel synth_intel: a10gx -> arria10gx 2019-12-10 13:48:10 +00:00
sf2 Revert "synth_* with -retime option now calls abc with -D 1 as well" 2019-04-18 07:59:16 -07:00
xilinx Refactoring memory attribute matching based on IEEE 1364.1 and Tool specific 2019-12-13 15:43:24 -06:00
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00