mirror of https://github.com/YosysHQ/yosys.git
225 lines
6.3 KiB
C++
225 lines
6.3 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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bool check_label(bool &active, std::string run_from, std::string run_to, std::string label)
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{
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if (!run_from.empty() && run_from == run_to) {
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active = (label == run_from);
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} else {
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if (label == run_from)
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active = true;
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if (label == run_to)
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active = false;
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}
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return active;
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}
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struct SynthPass : public Pass {
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SynthPass() : Pass("synth", "generic synthesis script") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" synth [options]\n");
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log("\n");
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log("This command runs the default synthesis script. This command does not operate\n");
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log("on partly selected designs.\n");
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log("\n");
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log(" -top <module>\n");
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log(" use the specified module as top module (default='top')\n");
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log("\n");
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log(" -encfile <file>\n");
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log(" passed to 'fsm_recode' via 'fsm'\n");
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log("\n");
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log(" -nofsm\n");
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log(" do not run FSM optimization\n");
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log("\n");
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log(" -noabc\n");
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log(" do not run abc (as if yosys was compiled without ABC support)\n");
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log("\n");
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log(" -noalumacc\n");
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log(" do not run 'alumacc' pass. i.e. keep arithmetic operators in\n");
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log(" their direct form ($add, $sub, etc.).\n");
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log("\n");
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log(" -nordff\n");
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log(" passed to 'memory'. prohibits merging of FFs into memory read ports\n");
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log("\n");
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log(" -run <from_label>[:<to_label>]\n");
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log(" only run the commands between the labels (see below). an empty\n");
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log(" from label is synonymous to 'begin', and empty to label is\n");
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log(" synonymous to the end of the command list.\n");
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log("\n");
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log("\n");
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log("The following commands are executed by this synthesis command:\n");
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log("\n");
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log(" begin:\n");
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log(" hierarchy -check [-top <top>]\n");
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log("\n");
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log(" coarse:\n");
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log(" proc\n");
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log(" opt_clean\n");
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log(" check\n");
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log(" opt\n");
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log(" wreduce\n");
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log(" alumacc\n");
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log(" share\n");
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log(" opt\n");
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log(" fsm\n");
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log(" opt -fast\n");
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log(" memory -nomap\n");
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log(" opt_clean\n");
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log("\n");
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log(" fine:\n");
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log(" opt -fast -full\n");
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log(" memory_map\n");
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log(" opt -full\n");
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log(" techmap\n");
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log(" opt -fast\n");
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#ifdef YOSYS_ENABLE_ABC
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log(" abc -fast\n");
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log(" opt -fast\n");
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#endif
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log("\n");
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log(" check:\n");
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log(" hierarchy -check\n");
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log(" stat\n");
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log(" check\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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std::string top_module, fsm_opts, memory_opts;
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std::string run_from, run_to;
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bool noalumacc = false;
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bool nofsm = false;
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bool noabc = false;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-top" && argidx+1 < args.size()) {
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top_module = args[++argidx];
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continue;
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}
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if (args[argidx] == "-encfile" && argidx+1 < args.size()) {
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fsm_opts = " -encfile " + args[++argidx];
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continue;
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}
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if (args[argidx] == "-run" && argidx+1 < args.size()) {
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size_t pos = args[argidx+1].find(':');
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if (pos == std::string::npos) {
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run_from = args[++argidx];
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run_to = args[argidx];
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} else {
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run_from = args[++argidx].substr(0, pos);
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run_to = args[argidx].substr(pos+1);
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}
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continue;
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}
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if (args[argidx] == "-nofsm") {
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nofsm = true;
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continue;
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}
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if (args[argidx] == "-noabc") {
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noabc = true;
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continue;
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}
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if (args[argidx] == "-noalumacc") {
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noalumacc = true;
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continue;
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}
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if (args[argidx] == "-nordff") {
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memory_opts += " -nordff";
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (!design->full_selection())
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log_cmd_error("This comannd only operates on fully selected designs!\n");
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bool active = run_from.empty();
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log_header("Executing SYNTH pass.\n");
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log_push();
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if (check_label(active, run_from, run_to, "begin"))
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{
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if (top_module.empty())
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Pass::call(design, stringf("hierarchy -check"));
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else
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Pass::call(design, stringf("hierarchy -check -top %s", top_module.c_str()));
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}
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if (check_label(active, run_from, run_to, "coarse"))
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{
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Pass::call(design, "proc");
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Pass::call(design, "opt_clean");
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Pass::call(design, "check");
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Pass::call(design, "opt");
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Pass::call(design, "wreduce");
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if (!noalumacc)
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Pass::call(design, "alumacc");
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Pass::call(design, "share");
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Pass::call(design, "opt");
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if (!nofsm)
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Pass::call(design, "fsm" + fsm_opts);
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Pass::call(design, "opt -fast");
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Pass::call(design, "memory -nomap" + memory_opts);
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Pass::call(design, "opt_clean");
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}
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if (check_label(active, run_from, run_to, "fine"))
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{
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Pass::call(design, "opt -fast -full");
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Pass::call(design, "memory_map");
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Pass::call(design, "opt -full");
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Pass::call(design, "techmap");
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Pass::call(design, "opt -fast");
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if (!noabc) {
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#ifdef YOSYS_ENABLE_ABC
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Pass::call(design, "abc -fast");
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Pass::call(design, "opt -fast");
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#endif
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}
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}
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if (check_label(active, run_from, run_to, "check"))
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{
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Pass::call(design, "hierarchy -check");
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Pass::call(design, "stat");
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Pass::call(design, "check");
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}
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log_pop();
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}
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} SynthPass;
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PRIVATE_NAMESPACE_END
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