mirror of https://github.com/YosysHQ/yosys.git
36 lines
449 B
Verilog
36 lines
449 B
Verilog
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module NOT(A, Y);
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input A;
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output Y = ~A;
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endmodule
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module NAND(A, B, Y);
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input A, B;
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output Y = ~(A & B);
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endmodule
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module NOR(A, B, Y);
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input A, B;
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output Y = ~(A | B);
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endmodule
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module DFF(C, D, Q);
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input C, D;
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output reg Q;
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always @(posedge C)
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Q <= D;
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endmodule
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module DFFSR(C, D, Q, S, R);
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input C, D, S, R;
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output reg Q;
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always @(posedge C, posedge S, posedge R)
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if (S)
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Q <= 1'b1;
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else if (R)
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Q <= 1'b0;
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else
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Q <= D;
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endmodule
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