mirror of https://github.com/YosysHQ/yosys.git
521 lines
15 KiB
Verilog
521 lines
15 KiB
Verilog
module LUT1(output F, input I0);
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parameter [1:0] INIT = 0;
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assign F = I0 ? INIT[1] : INIT[0];
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endmodule
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module LUT2(output F, input I0, I1);
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parameter [3:0] INIT = 0;
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wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
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assign F = I0 ? s1[1] : s1[0];
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endmodule
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module LUT3(output F, input I0, I1, I2);
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parameter [7:0] INIT = 0;
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wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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assign F = I0 ? s1[1] : s1[0];
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endmodule
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module LUT4(output F, input I0, I1, I2, I3);
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parameter [15:0] INIT = 0;
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wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
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wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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assign F = I0 ? s1[1] : s1[0];
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endmodule
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module MUX2 (O, I0, I1, S0);
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input I0,I1;
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input S0;
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output O;
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assign O = S0 ? I1 : I0;
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endmodule
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module MUX2_LUT5 (O, I0, I1, S0);
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input I0,I1;
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input S0;
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output O;
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MUX2 mux2_lut5 (O, I0, I1, S0);
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endmodule
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module MUX2_LUT6 (O, I0, I1, S0);
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input I0,I1;
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input S0;
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output O;
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MUX2 mux2_lut6 (O, I0, I1, S0);
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endmodule
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module MUX2_LUT7 (O, I0, I1, S0);
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input I0,I1;
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input S0;
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output O;
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MUX2 mux2_lut7 (O, I0, I1, S0);
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endmodule
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module MUX2_LUT8 (O, I0, I1, S0);
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input I0,I1;
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input S0;
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output O;
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MUX2 mux2_lut8 (O, I0, I1, S0);
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endmodule
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module DFF (output reg Q, input CLK, D);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(posedge CLK)
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Q <= D;
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endmodule
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module DFFE (output reg Q, input D, CLK, CE);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(posedge CLK) begin
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if (CE)
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Q <= D;
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end
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endmodule // DFFE (positive clock edge; clock enable)
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module DFFS (output reg Q, input D, CLK, SET);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(posedge CLK) begin
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if (SET)
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Q <= 1'b1;
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else
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Q <= D;
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end
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endmodule // DFFS (positive clock edge; synchronous set)
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module DFFSE (output reg Q, input D, CLK, CE, SET);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(posedge CLK) begin
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if (SET)
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Q <= 1'b1;
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else if (CE)
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Q <= D;
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end
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endmodule // DFFSE (positive clock edge; synchronous set takes precedence over clock enable)
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module DFFR (output reg Q, input D, CLK, RESET);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(posedge CLK) begin
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if (RESET)
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Q <= 1'b0;
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else
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Q <= D;
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end
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endmodule // DFFR (positive clock edge; synchronous reset)
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module DFFRE (output reg Q, input D, CLK, CE, RESET);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(posedge CLK) begin
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if (RESET)
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Q <= 1'b0;
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else if (CE)
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Q <= D;
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end
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endmodule // DFFRE (positive clock edge; synchronous reset takes precedence over clock enable)
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module DFFP (output reg Q, input D, CLK, PRESET);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(posedge CLK or posedge PRESET) begin
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if(PRESET)
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Q <= 1'b1;
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else
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Q <= D;
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end
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endmodule // DFFP (positive clock edge; asynchronous preset)
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module DFFPE (output reg Q, input D, CLK, CE, PRESET);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(posedge CLK or posedge PRESET) begin
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if(PRESET)
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Q <= 1'b1;
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else if (CE)
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Q <= D;
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end
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endmodule // DFFPE (positive clock edge; asynchronous preset; clock enable)
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module DFFC (output reg Q, input D, CLK, CLEAR);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(posedge CLK or posedge CLEAR) begin
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if(CLEAR)
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Q <= 1'b0;
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else
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Q <= D;
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end
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endmodule // DFFC (positive clock edge; asynchronous clear)
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module DFFCE (output reg Q, input D, CLK, CE, CLEAR);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(posedge CLK or posedge CLEAR) begin
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if(CLEAR)
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Q <= 1'b0;
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else if (CE)
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Q <= D;
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end
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endmodule // DFFCE (positive clock edge; asynchronous clear; clock enable)
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module DFFN (output reg Q, input CLK, D);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(negedge CLK)
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Q <= D;
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endmodule
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module DFFNE (output reg Q, input D, CLK, CE);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(negedge CLK) begin
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if (CE)
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Q <= D;
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end
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endmodule // DFFNE (negative clock edge; clock enable)
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module DFFNS (output reg Q, input D, CLK, SET);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(negedge CLK) begin
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if (SET)
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Q <= 1'b1;
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else
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Q <= D;
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end
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endmodule // DFFNS (negative clock edge; synchronous set)
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module DFFNSE (output reg Q, input D, CLK, CE, SET);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(negedge CLK) begin
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if (SET)
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Q <= 1'b1;
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else if (CE)
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Q <= D;
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end
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endmodule // DFFNSE (negative clock edge; synchronous set takes precedence over clock enable)
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module DFFNR (output reg Q, input D, CLK, RESET);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(negedge CLK) begin
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if (RESET)
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Q <= 1'b0;
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else
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Q <= D;
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end
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endmodule // DFFNR (negative clock edge; synchronous reset)
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module DFFNRE (output reg Q, input D, CLK, CE, RESET);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(negedge CLK) begin
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if (RESET)
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Q <= 1'b0;
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else if (CE)
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Q <= D;
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end
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endmodule // DFFNRE (negative clock edge; synchronous reset takes precedence over clock enable)
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module DFFNP (output reg Q, input D, CLK, PRESET);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(negedge CLK or posedge PRESET) begin
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if(PRESET)
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Q <= 1'b1;
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else
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Q <= D;
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end
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endmodule // DFFNP (negative clock edge; asynchronous preset)
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module DFFNPE (output reg Q, input D, CLK, CE, PRESET);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(negedge CLK or posedge PRESET) begin
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if(PRESET)
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Q <= 1'b1;
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else if (CE)
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Q <= D;
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end
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endmodule // DFFNPE (negative clock edge; asynchronous preset; clock enable)
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module DFFNC (output reg Q, input D, CLK, CLEAR);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(negedge CLK or posedge CLEAR) begin
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if(CLEAR)
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Q <= 1'b0;
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else
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Q <= D;
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end
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endmodule // DFFNC (negative clock edge; asynchronous clear)
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module DFFNCE (output reg Q, input D, CLK, CE, CLEAR);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(negedge CLK or posedge CLEAR) begin
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if(CLEAR)
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Q <= 1'b0;
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else if (CE)
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Q <= D;
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end
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endmodule // DFFNCE (negative clock edge; asynchronous clear; clock enable)
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// TODO add more DFF sim cells
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module VCC(output V);
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assign V = 1;
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endmodule
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module GND(output G);
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assign G = 0;
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endmodule
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module IBUF(output O, input I);
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assign O = I;
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endmodule
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module OBUF(output O, input I);
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assign O = I;
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endmodule
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module TBUF (O, I, OEN);
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input I, OEN;
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output O;
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assign O = OEN ? I : 1'bz;
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endmodule
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module IOBUF (O, IO, I, OEN);
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input I,OEN;
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output O;
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inout IO;
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assign IO = OEN ? I : 1'bz;
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assign I = IO;
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endmodule
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module GSR (input GSRI);
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wire GSRO = GSRI;
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endmodule
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module ALU (SUM, COUT, I0, I1, I3, CIN);
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input I0;
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input I1;
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input I3;
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input CIN;
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output SUM;
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output COUT;
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localparam ADD = 0;
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localparam SUB = 1;
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localparam ADDSUB = 2;
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localparam NE = 3;
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localparam GE = 4;
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localparam LE = 5;
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localparam CUP = 6;
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localparam CDN = 7;
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localparam CUPCDN = 8;
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localparam MULT = 9;
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parameter ALU_MODE = 0;
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reg S, C;
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assign SUM = S ^ CIN;
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assign COUT = S? CIN : C;
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always @* begin
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case (ALU_MODE)
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ADD: begin
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S = I0 ^ I1;
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C = I0;
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end
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SUB: begin
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S = I0 ^ ~I1;
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C = I0;
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end
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ADDSUB: begin
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S = I3? I0 ^ I1 : I0 ^ ~I1;
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C = I0;
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end
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NE: begin
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S = I0 ^ ~I1;
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C = 1'b1;
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end
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GE: begin
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S = I0 ^ ~I1;
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C = I0;
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end
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LE: begin
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S = ~I0 ^ I1;
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C = I1;
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end
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CUP: begin
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S = I0;
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C = 1'b0;
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end
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CDN: begin
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S = ~I0;
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C = 1'b1;
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end
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CUPCDN: begin
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S = I3? I0 : ~I0;
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C = I0;
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end
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MULT: begin
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S = I0 & I1;
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C = I0 & I1;
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end
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endcase
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end
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endmodule
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module RAM16S4 (DO, DI, AD, WRE, CLK);
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parameter WIDTH = 4;
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parameter INIT_0 = 16'h0000;
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parameter INIT_1 = 16'h0000;
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parameter INIT_2 = 16'h0000;
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parameter INIT_3 = 16'h0000;
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input [WIDTH-1:0] AD;
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input [WIDTH-1:0] DI;
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output [WIDTH-1:0] DO;
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input CLK;
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input WRE;
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reg [15:0] mem0, mem1, mem2, mem3;
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initial begin
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mem0 = INIT_0;
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mem1 = INIT_1;
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mem2 = INIT_2;
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mem3 = INIT_3;
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end
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assign DO[0] = mem0[AD];
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assign DO[1] = mem1[AD];
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assign DO[2] = mem2[AD];
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assign DO[3] = mem3[AD];
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always @(posedge CLK) begin
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if (WRE) begin
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mem0[AD] <= DI[0];
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mem1[AD] <= DI[1];
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mem2[AD] <= DI[2];
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mem3[AD] <= DI[3];
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end
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end
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endmodule // RAM16S4
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(* blackbox *)
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module SDP (DO, DI, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCE, RESETA, RESETB);
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//1'b0: Bypass mode; 1'b1 Pipeline mode
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parameter READ_MODE = 1'b0;
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parameter BIT_WIDTH_0 = 32; // 1, 2, 4, 8, 16, 32
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parameter BIT_WIDTH_1 = 32; // 1, 2, 4, 8, 16, 32
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parameter BLK_SEL = 3'b000;
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parameter RESET_MODE = "SYNC";
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parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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input CLKA, CEA, CLKB, CEB;
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input OCE; // clock enable of memory output register
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input RESETA, RESETB; // resets output registers, not memory contents
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input WREA, WREB; // 1'b0: read enabled; 1'b1: write enabled
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input [13:0] ADA, ADB;
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input [31:0] DI;
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input [2:0] BLKSEL;
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output [31:0] DO;
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endmodule
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