mirror of https://github.com/YosysHQ/yosys.git
474 lines
14 KiB
C++
474 lines
14 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) Martin Povišer <povik@cutebit.org>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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uint32_t read_be32(std::istream &f) {
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return ((uint32_t) f.get() << 24) |
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((uint32_t) f.get() << 16) |
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((uint32_t) f.get() << 8) | (uint32_t) f.get();
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}
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IdString read_idstring(std::istream &f)
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{
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std::string str;
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std::getline(f, str, '\0');
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if (!f.good())
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log_error("failed to read string\n");
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return RTLIL::escape_id(str);
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}
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struct Xaiger2Frontend : public Frontend {
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Xaiger2Frontend() : Frontend("xaiger2", "(experimental) read XAIGER file")
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{
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experimental();
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}
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" read_xaiger2 -sc_mapping [options] <filename>\n");
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log("\n");
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log("Read a standard cell mapping from a XAIGER file into an existing module.\n");
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log("\n");
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log(" -module_name <name>\n");
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log(" name of the target module\n");
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log("\n");
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log(" -map2 <filename>\n");
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log(" read file with symbol information\n");
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log("\n");
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}
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void read_sc_mapping(std::istream *&f, std::string filename, std::vector<std::string> args, Design *design)
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{
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IdString module_name;
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std::string map_filename;
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size_t argidx;
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for (argidx = 2; argidx < args.size(); argidx++) {
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std::string arg = args[argidx];
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if (arg == "-module_name" && argidx + 1 < args.size()) {
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module_name = RTLIL::escape_id(args[++argidx]);
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continue;
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}
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if (arg == "-map2" && argidx + 1 < args.size()) {
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map_filename = args[++argidx];
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continue;
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}
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break;
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}
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extra_args(f, filename, args, argidx, true);
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if (map_filename.empty())
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log_error("A '-map2' argument required\n");
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if (module_name.empty())
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log_error("A '-module_name' argument required\n");
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Module *module = design->module(module_name);
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if (!module)
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log_error("Module '%s' not found\n", log_id(module_name));
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std::ifstream map_file;
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map_file.open(map_filename);
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if (!map_file)
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log_error("Failed to open map file '%s'\n", map_filename.c_str());
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unsigned int M, I, L, O, A;
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std::string header;
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if (!(*f >> header >> M >> I >> L >> O >> A) || header != "aig")
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log_error("Bad header\n");
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std::string line;
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std::getline(*f, line);
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log_debug("M=%u I=%u L=%u O=%u A=%u\n", M, I, L, O, A);
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if (L != 0)
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log_error("Latches unsupported\n");
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if (I + L + A != M)
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log_error("Inconsistent header\n");
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std::vector<int> outputs;
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for (int i = 0; i < (int) O; i++) {
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int po;
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*f >> po;
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log_assert(f->get() == '\n');
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outputs.push_back(po);
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}
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std::vector<std::pair<Cell *, Module *>> boxes;
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std::vector<bool> retained_boxes;
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std::vector<SigBit> bits(2 + 2*M, RTLIL::Sm);
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bits[0] = RTLIL::S0;
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bits[1] = RTLIL::S1;
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std::string type;
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while (map_file >> type) {
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if (type == "pi") {
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int pi_idx;
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int woffset;
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std::string name;
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if (!(map_file >> pi_idx >> woffset >> name))
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log_error("Bad map file (1)\n");
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int lit = (2 * pi_idx) + 2;
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if (lit < 0 || lit >= (int) bits.size())
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log_error("Bad map file (2)\n");
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Wire *w = module->wire(name);
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if (!w || woffset < 0 || woffset >= w->width)
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log_error("Map file references non-existent signal bit %s[%d]\n",
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name.c_str(), woffset);
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bits[lit] = SigBit(w, woffset);
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} else if (type == "box") {
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int box_seq;
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std::string name;
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if (!(map_file >> box_seq >> name))
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log_error("Bad map file (20)\n");
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if (box_seq < 0)
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log_error("Bad map file (21)\n");
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Cell *box = module->cell(RTLIL::escape_id(name));
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if (!box)
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log_error("Map file references non-existent box %s\n",
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name.c_str());
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Module *def = design->module(box->type);
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if (def && !box->parameters.empty()) {
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// TODO: This is potentially costly even if a cached derivation exists
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def = design->module(def->derive(design, box->parameters));
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log_assert(def);
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}
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if (!def)
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log_error("Bad map file (22)\n");
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if (box_seq >= (int) boxes.size()) {
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boxes.resize(box_seq + 1);
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retained_boxes.resize(box_seq + 1);
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}
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boxes[box_seq] = std::make_pair(box, def);
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} else {
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std::string scratch;
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std::getline(map_file, scratch);
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}
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}
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for (int i = 0; i < (int) A; i++) {
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while (f->get() & 0x80 && !f->eof());
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while (f->get() & 0x80 && !f->eof());
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}
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if (f->get() != 'c')
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log_error("Missing 'c' ahead of extensions\n");
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if (f->peek() == '\n')
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f->get();
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auto extensions_start = f->tellg();
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log_debug("reading 'h' (first pass)\n");
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for (int c = f->get(); c != EOF; c = f->get()) {
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if (c == 'h') {
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uint32_t len, ci_num, co_num, pi_num, po_num, no_boxes;
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len = read_be32(*f);
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read_be32(*f);
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ci_num = read_be32(*f);
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co_num = read_be32(*f);
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pi_num = read_be32(*f);
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po_num = read_be32(*f);
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no_boxes = read_be32(*f);
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log_debug("len=%u ci_num=%u co_num=%u pi_num=%u po_nun=%u no_boxes=%u\n",
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len, ci_num, co_num, pi_num, po_num, no_boxes);
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int ci_counter = 0;
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for (uint32_t i = 0; i < no_boxes; i++) {
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uint32_t box_inputs, box_outputs, box_id, box_seq;
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box_inputs = read_be32(*f);
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box_outputs = read_be32(*f);
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box_id = read_be32(*f);
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box_seq = read_be32(*f);
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log("box_seq=%d boxes.size=%d\n", box_seq, (int) boxes.size());
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log_assert(box_seq < boxes.size());
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auto [cell, def] = boxes[box_seq];
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log_assert(cell && def);
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retained_boxes[box_seq] = true;
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int box_ci_idx = 0;
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for (auto port_id : def->ports) {
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Wire *port = def->wire(port_id);
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if (port->port_output) {
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if (!cell->hasPort(port_id) || cell->getPort(port_id).size() != port->width)
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log_error("Malformed design (1)\n");
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SigSpec &conn = cell->connections_[port_id];
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for (int j = 0; j < port->width; j++) {
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if (conn[j].wire && conn[j].wire->port_output)
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conn[j] = module->addWire(module->uniquify(
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stringf("$box$%s$%s$%d",
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cell->name.isPublic() ? cell->name.c_str() + 1 : cell->name.c_str(),
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port_id.isPublic() ? port_id.c_str() + 1 : port_id.c_str(),
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j)));
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bits[2*(pi_num + ci_counter + box_ci_idx++) + 2] = conn[j];
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}
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}
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}
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log_assert(box_ci_idx == (int) box_outputs);
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ci_counter += box_ci_idx;
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}
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log_assert(pi_num + ci_counter == ci_num);
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} else if (c == '\n') {
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break;
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} else if (c == 'c') {
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break;
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} else {
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uint32_t len = read_be32(*f);
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f->ignore(len);
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log_debug(" section '%c' (%d): ignoring %d bytes\n", c, c, len);
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}
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}
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log_debug("reading 'M' (second pass)\n");
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f->seekg(extensions_start);
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bool read_mapping = false;
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uint32_t no_cells, no_instances;
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for (int c = f->get(); c != EOF; c = f->get()) {
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if (c == 'M') {
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uint32_t len = read_be32(*f);
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read_mapping = true;
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no_cells = read_be32(*f);
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no_instances = read_be32(*f);
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log_debug("M: len=%u no_cells=%u no_instances=%u\n", len, no_cells, no_instances);
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struct MappingCell {
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RTLIL::IdString type;
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RTLIL::IdString out;
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std::vector<RTLIL::IdString> ins;
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};
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std::vector<MappingCell> cells;
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cells.resize(no_cells);
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for (unsigned i = 0; i < no_cells; ++i) {
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auto &cell = cells[i];
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cell.type = read_idstring(*f);
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cell.out = read_idstring(*f);
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uint32_t nins = read_be32(*f);
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for (uint32_t j = 0; j < nins; j++)
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cell.ins.push_back(read_idstring(*f));
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log_debug("M: Cell %s (out %s, ins", log_id(cell.type), log_id(cell.out));
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for (auto in : cell.ins)
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log_debug(" %s", log_id(in));
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log_debug(")\n");
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}
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for (unsigned i = 0; i < no_instances; ++i) {
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uint32_t cell_id = read_be32(*f);
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uint32_t out_lit = read_be32(*f);
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log_assert(out_lit < bits.size());
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log_assert(bits[out_lit] == RTLIL::Sm);
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log_assert(cell_id < cells.size());
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auto &cell = cells[cell_id];
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Cell *instance = module->addCell(module->uniquify(stringf("$sc%d", out_lit)), cell.type);
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auto out_w = module->addWire(module->uniquify(stringf("$lit%d", out_lit)));
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instance->setPort(cell.out, out_w);
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bits[out_lit] = out_w;
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for (auto in : cell.ins) {
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uint32_t in_lit = read_be32(*f);
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log_assert(out_lit < bits.size());
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log_assert(bits[in_lit] != RTLIL::Sm);
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instance->setPort(in, bits[in_lit]);
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}
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}
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} else if (c == '\n') {
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break;
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} else if (c == 'c') {
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break;
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} else {
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uint32_t len = read_be32(*f);
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f->ignore(len);
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log_debug(" section '%c' (%d): ignoring %d bytes\n", c, c, len);
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}
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}
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if (!read_mapping)
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log_error("Missing mapping (no 'M' section)\n");
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log("Read %d instances with cell library of size %d.\n",
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no_instances, no_cells);
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f->seekg(extensions_start);
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log_debug("reading 'h' (second pass)\n");
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int co_counter = 0;
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for (int c = f->get(); c != EOF; c = f->get()) {
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if (c == 'h') {
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uint32_t len, ci_num, co_num, pi_num, po_num, no_boxes;
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len = read_be32(*f);
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read_be32(*f);
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ci_num = read_be32(*f);
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co_num = read_be32(*f);
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pi_num = read_be32(*f);
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po_num = read_be32(*f);
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no_boxes = read_be32(*f);
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log_debug("len=%u ci_num=%u co_num=%u pi_num=%u po_nun=%u no_boxes=%u\n",
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len, ci_num, co_num, pi_num, po_num, no_boxes);
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for (uint32_t i = 0; i < no_boxes; i++) {
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uint32_t box_inputs, box_outputs, box_id, box_seq;
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box_inputs = read_be32(*f);
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box_outputs = read_be32(*f);
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box_id = read_be32(*f);
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box_seq = read_be32(*f);
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log("box_seq=%d boxes.size=%d\n", box_seq, (int) boxes.size());
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log_assert(box_seq < boxes.size());
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auto [cell, def] = boxes[box_seq];
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log_assert(cell && def);
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int box_co_idx = 0;
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for (auto port_id : def->ports) {
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Wire *port = def->wire(port_id);
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SigSpec conn;
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if (port->port_input) {
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if (!cell->hasPort(port_id) || cell->getPort(port_id).size() != port->width)
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log_error("Malformed design (2)\n");
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SigSpec conn;
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for (int j = 0; j < port->width; j++) {
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log_assert(co_counter + box_co_idx < (int) outputs.size());
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int lit = outputs[co_counter + box_co_idx++];
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log_assert(lit >= 0 && lit < (int) bits.size());
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SigBit bit = bits[lit];
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if (bit == RTLIL::Sm)
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log_error("Malformed mapping (1)\n");
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conn.append(bit);
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}
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cell->setPort(port_id, conn);
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}
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}
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log_assert(box_co_idx == (int) box_inputs);
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co_counter += box_co_idx;
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}
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log_assert(po_num + co_counter == co_num);
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} else if (c == '\n') {
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break;
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} else if (c == 'c') {
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break;
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} else {
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uint32_t len = read_be32(*f);
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f->ignore(len);
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log_debug(" section '%c' (%d): ignoring %d bytes\n", c, c, len);
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}
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}
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while (true) {
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std::string scratch;
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std::getline(*f, scratch);
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if (f->eof())
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break;
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log_assert(!f->fail());
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log("input file: %s\n", scratch.c_str());
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}
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log_debug("co_counter=%d\n", co_counter);
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// TODO: seek without close/open
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map_file.close();
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map_file.open(map_filename);
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while (map_file >> type) {
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if (type == "po") {
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int po_idx;
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int woffset;
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std::string name;
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if (!(map_file >> po_idx >> woffset >> name))
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log_error("Bad map file (3)\n");
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po_idx += co_counter;
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if (po_idx < 0 || po_idx >= (int) outputs.size())
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log_error("Bad map file (4)\n");
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int lit = outputs[po_idx];
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if (lit < 0 || lit >= (int) bits.size())
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log_error("Bad map file (5)\n");
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if (bits[lit] == RTLIL::Sm)
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log_error("Bad map file (6)\n");
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Wire *w = module->wire(name);
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if (!w || woffset < 0 || woffset >= w->width)
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log_error("Map file references non-existent signal bit %s[%d]\n",
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name.c_str(), woffset);
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module->connect(SigBit(w, woffset), bits[lit]);
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} else if (type == "pseudopo") {
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int po_idx;
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int poffset;
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std::string box_name;
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std::string box_port;
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if (!(map_file >> po_idx >> poffset >> box_name >> box_port))
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log_error("Bad map file (7)\n");
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po_idx += co_counter;
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if (po_idx < 0 || po_idx >= (int) outputs.size())
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log_error("Bad map file (8)\n");
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int lit = outputs[po_idx];
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if (lit < 0 || lit >= (int) bits.size())
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log_error("Bad map file (9)\n");
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if (bits[lit] == RTLIL::Sm)
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log_error("Bad map file (10)\n");
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Cell *cell = module->cell(box_name);
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if (!cell || !cell->hasPort(box_port))
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log_error("Map file references non-existent box port %s/%s\n",
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box_name.c_str(), box_port.c_str());
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SigSpec &port = cell->connections_[box_port];
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if (poffset < 0 || poffset >= port.size())
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log_error("Map file references non-existent box port bit %s/%s[%d]\n",
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box_name.c_str(), box_port.c_str(), poffset);
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port[poffset] = bits[lit];
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} else {
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std::string scratch;
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std::getline(map_file, scratch);
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}
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}
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int box_seq = 0;
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for (auto [cell, def] : boxes) {
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if (!retained_boxes[box_seq++])
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module->remove(cell);
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}
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}
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void execute(std::istream *&f, std::string filename, std::vector<std::string> args, Design *design) override
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{
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log_header(design, "Executing XAIGER2 frontend.\n");
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if (args.size() > 1 && args[1] == "-sc_mapping") {
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read_sc_mapping(f, filename, args, design);
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return;
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}
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|
|
log_cmd_error("Mode '-sc_mapping' must be selected\n");
|
|
}
|
|
} Xaiger2Frontend;
|
|
|
|
PRIVATE_NAMESPACE_END
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