mirror of https://github.com/YosysHQ/yosys.git
23 lines
388 B
Verilog
23 lines
388 B
Verilog
// Exact reproduction of Figure 2(a) from 10.1109/43.273754.
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module top(...);
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input a,b,c,d,e,f;
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wire nA = b&c;
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wire A = !nA;
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wire nB = c|d;
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wire B = !nB;
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wire nC = e&f;
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wire C = !nC;
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wire D = A|B;
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wire E = a&D;
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wire nF = D&C;
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wire F = !nF;
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wire nG = F|B;
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wire G = !nG;
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wire H = a&F;
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wire I = E|G;
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wire J = G&C;
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wire np = H&I;
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output p = !np;
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output q = A|J;
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endmodule
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