yosys/passes
Clifford Wolf 2185125760 Added missing ct_all setup to opt_clean 2015-08-11 07:54:32 +02:00
..
cmds Fixed "check" command for inout ports 2015-07-27 09:54:58 +02:00
equiv Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
fsm Bugfix in fsm_extract 2015-07-03 18:42:36 +02:00
hierarchy Keep modules with $assume (like $assert) 2015-07-25 12:09:57 +02:00
memory Use MEMID as name for $mem cell 2015-08-09 13:35:44 +02:00
opt Added missing ct_all setup to opt_clean 2015-08-11 07:54:32 +02:00
proc Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
sat Added "miter -assert" 2015-07-25 12:09:57 +02:00
techmap Fixed flatten $meminit handling 2015-07-30 21:43:41 +02:00
tests Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00