mirror of https://github.com/YosysHQ/yosys.git
69 lines
2.8 KiB
Plaintext
69 lines
2.8 KiB
Plaintext
read_verilog <<EOT
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module fastfir_dynamictaps(i_clk, i_reset, i_tap_wr, i_tap, i_ce, i_sample, o_result);
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wire [30:0] _00_;
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wire [23:0] _01_;
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wire [11:0] _02_;
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wire [30:0] _03_;
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wire [23:0] _04_;
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wire [30:0] _05_;
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wire [23:0] _06_;
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wire [30:0] _07_;
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wire [23:0] _08_;
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wire [11:0] _09_;
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wire [30:0] _10_;
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wire [23:0] _11_;
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wire [30:0] _12_;
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wire [23:0] _13_;
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wire [11:0] \fir.FILTER[0].tapk.delayed_sample ;
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reg [30:0] \fir.FILTER[0].tapk.o_acc = 31'h00000000;
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wire [11:0] \fir.FILTER[0].tapk.o_sample ;
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reg [23:0] \fir.FILTER[0].tapk.product ;
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reg [11:0] \fir.FILTER[0].tapk.tap = 12'h000;
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wire [11:0] \fir.FILTER[1].tapk.delayed_sample ;
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wire [30:0] \fir.FILTER[1].tapk.o_acc ;
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wire [11:0] \fir.FILTER[1].tapk.o_sample ;
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reg [23:0] \fir.FILTER[1].tapk.product ;
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reg [11:0] \fir.FILTER[1].tapk.tap = 12'h000;
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input i_ce;
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input i_clk;
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input i_reset;
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input [11:0] i_sample;
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input [11:0] i_tap;
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input i_tap_wr;
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output [30:0] o_result;
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reg [30:0] o_result;
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assign _03_ = 31'h00000000 + { \fir.FILTER[0].tapk.product [23], \fir.FILTER[0].tapk.product [23], \fir.FILTER[0].tapk.product [23], \fir.FILTER[0].tapk.product [23], \fir.FILTER[0].tapk.product [23], \fir.FILTER[0].tapk.product [23], \fir.FILTER[0].tapk.product [23], \fir.FILTER[0].tapk.product };
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assign _04_ = $signed(\fir.FILTER[0].tapk.tap ) * $signed(i_sample);
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always @(posedge i_clk)
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\fir.FILTER[0].tapk.tap <= _02_;
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always @(posedge i_clk)
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\fir.FILTER[0].tapk.o_acc <= _00_;
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always @(posedge i_clk)
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\fir.FILTER[0].tapk.product <= _01_;
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assign _02_ = i_tap_wr ? i_tap : \fir.FILTER[0].tapk.tap ;
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assign _05_ = i_ce ? _03_ : \fir.FILTER[0].tapk.o_acc ;
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assign _00_ = i_reset ? 31'h00000000 : _05_;
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assign _06_ = i_ce ? _04_ : \fir.FILTER[0].tapk.product ;
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assign _01_ = i_reset ? 24'h000000 : _06_;
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assign _10_ = \fir.FILTER[0].tapk.o_acc + { \fir.FILTER[1].tapk.product [23], \fir.FILTER[1].tapk.product [23], \fir.FILTER[1].tapk.product [23], \fir.FILTER[1].tapk.product [23], \fir.FILTER[1].tapk.product [23], \fir.FILTER[1].tapk.product [23], \fir.FILTER[1].tapk.product [23], \fir.FILTER[1].tapk.product };
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assign _11_ = $signed(\fir.FILTER[1].tapk.tap ) * $signed(i_sample);
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always @(posedge i_clk)
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\fir.FILTER[1].tapk.tap <= _09_;
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always @(posedge i_clk)
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o_result <= _07_;
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always @(posedge i_clk)
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\fir.FILTER[1].tapk.product <= _08_;
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assign _09_ = i_tap_wr ? \fir.FILTER[0].tapk.tap : \fir.FILTER[1].tapk.tap ;
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assign _12_ = i_ce ? _10_ : o_result;
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assign _07_ = i_reset ? 31'h00000000 : _12_;
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assign _13_ = i_ce ? _11_ : \fir.FILTER[1].tapk.product ;
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assign _08_ = i_reset ? 24'h000000 : _13_;
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assign \fir.FILTER[1].tapk.o_acc = o_result;
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endmodule
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EOT
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synth_xilinx -abc9
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cd fastfir_dynamictaps
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select -assert-count 2 t:DSP48E1
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select -assert-none t:* t:DSP48E1 %d t:BUFG %d
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