mirror of https://github.com/YosysHQ/yosys.git
261 lines
7.1 KiB
ReStructuredText
261 lines
7.1 KiB
ReStructuredText
.. _chapter:prog:
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Writing extensions
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==================
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.. TODO: copypaste
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This chapter contains some bits and pieces of information about programming
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yosys extensions. Don't be afraid to ask questions on the YosysHQ Slack.
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Guidelines
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----------
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The guidelines directory contains notes on various aspects of Yosys development.
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The files GettingStarted and CodingStyle may be of particular interest, and are
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reproduced here.
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.. literalinclude:: ../temp/GettingStarted
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:language: none
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:caption: guidelines/GettingStarted
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.. literalinclude:: ../temp/CodingStyle
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:language: none
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:caption: guidelines/CodingStyle
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The "stubsnets" example module
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------------------------------
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The following is the complete code of the "stubsnets" example module. It is
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included in the Yosys source distribution as
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``docs/source/CHAPTER_Prog/stubnets.cc``.
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.. literalinclude:: ../CHAPTER_Prog/stubnets.cc
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:language: c++
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:linenos:
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:caption: docs/source/CHAPTER_Prog/stubnets.cc
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.. literalinclude:: ../CHAPTER_Prog/Makefile
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:language: makefile
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:linenos:
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:caption: docs/source/CHAPTER_Prog/Makefile
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.. literalinclude:: ../CHAPTER_Prog/test.v
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:language: verilog
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:linenos:
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:caption: docs/source/CHAPTER_Prog/test.v
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Quick guide
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-----------
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See also: ``docs/resources/PRESENTATION_Prog/*``.
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Program components and data formats
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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See :doc:`/yosys_internals/formats/rtlil_rep` document for more information
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about the internal data storage format used in Yosys and the classes that it
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provides.
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This document will focus on the much simpler version of RTLIL left after the
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commands ``proc`` and ``memory`` (or ``memory -nomap``):
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.. figure:: ../../images/simplified_rtlil.*
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:class: width-helper
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:name: fig:Simplified_RTLIL
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Simplified RTLIL entity-relationship diagram without memories and processes
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It is possible to only work on this simpler version:
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.. code:: c++
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for (RTLIL::Module *module : design->selected_modules() {
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if (module->has_memories_warn() || module->has_processes_warn())
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continue;
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....
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}
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When trying to understand what a command does, creating a small test case to
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look at the output of ``dump`` and ``show`` before and after the command has
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been executed can be helpful. The :doc:`/using_yosys/selections` document has
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more information on using these commands.
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.. TODO: copypaste
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Creating modules from scratch
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Let's create the following module using the RTLIL API:
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.. code:: Verilog
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module absval(input signed [3:0] a, output [3:0] y);
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assign y = a[3] ? -a : a;
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endmodule
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.. code:: C++
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RTLIL::Module *module = new RTLIL::Module;
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module->name = "\\absval";
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RTLIL::Wire *a = module->addWire("\\a", 4);
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a->port_input = true;
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a->port_id = 1;
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RTLIL::Wire *y = module->addWire("\\y", 4);
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y->port_output = true;
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y->port_id = 2;
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RTLIL::Wire *a_inv = module->addWire(NEW_ID, 4);
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module->addNeg(NEW_ID, a, a_inv, true);
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module->addMux(NEW_ID, a, a_inv, RTLIL::SigSpec(a, 1, 3), y);
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module->fixup_ports();
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Modifying modules
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~~~~~~~~~~~~~~~~~
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Most commands modify existing modules, not create new ones.
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When modifying existing modules, stick to the following DOs and DON'Ts:
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- Do not remove wires. Simply disconnect them and let a successive ``clean``
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command worry about removing it.
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- Use ``module->fixup_ports()`` after changing the ``port_*`` properties of
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wires.
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- You can safely remove cells or change the ``connections`` property of a cell,
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but be careful when changing the size of the ``SigSpec`` connected to a cell
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port.
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- Use the ``SigMap`` helper class (see next slide) when you need a unique handle for each signal bit.
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Using the SigMap helper class
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Consider the following module:
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.. code:: Verilog
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module test(input a, output x, y);
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assign x = a, y = a;
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endmodule
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In this case ``a``, ``x``, and ``y`` are all different names for the same signal. However:
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.. code:: C++
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RTLIL::SigSpec a(module->wire("\\a")), x(module->wire("\\x")),
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y(module->wire("\\y"));
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log("%d %d %d\n", a == x, x == y, y == a); // will print "0 0 0"
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The ``SigMap`` helper class can be used to map all such aliasing signals to a
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unique signal from the group (usually the wire that is directly driven by a cell or port).
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.. code:: C++
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SigMap sigmap(module);
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log("%d %d %d\n", sigmap(a) == sigmap(x), sigmap(x) == sigmap(y),
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sigmap(y) == sigmap(a)); // will print "1 1 1"
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Printing log messages
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~~~~~~~~~~~~~~~~~~~~~
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The ``log()`` function is a ``printf()``-like function that can be used to create log messages.
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Use ``log_signal()`` to create a C-string for a SigSpec object:
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.. code:: C++
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log("Mapped signal x: %s\n", log_signal(sigmap(x)));
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The pointer returned by ``log_signal()`` is automatically freed by the log
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framework at a later time.
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Use ``log_id()`` to create a C-string for an ``RTLIL::IdString``:
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.. code:: C++
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log("Name of this module: %s\n", log_id(module->name));
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Use ``log_header()`` and ``log_push()``/``log_pop()`` to structure log messages:
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.. code:: C++
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log_header(design, "Doing important stuff!\n");
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log_push();
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for (int i = 0; i < 10; i++)
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log("Log message #%d.\n", i);
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log_pop();
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Error handling
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~~~~~~~~~~~~~~
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Use ``log_error()`` to report a non-recoverable error:
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.. code:: C++
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if (design->modules.count(module->name) != 0)
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log_error("A module with the name %s already exists!\n",
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RTLIL::id2cstr(module->name));
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Use ``log_cmd_error()`` to report a recoverable error:
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.. code:: C++
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if (design->selection_stack.back().empty())
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log_cmd_error("This command can't operator on an empty selection!\n");
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Use ``log_assert()`` and ``log_abort()`` instead of ``assert()`` and ``abort()``.
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Creating a command
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~~~~~~~~~~~~~~~~~~
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Simply create a global instance of a class derived from ``Pass`` to create
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a new yosys command:
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.. code:: C++
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#include "kernel/yosys.h"
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USING_YOSYS_NAMESPACE
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struct MyPass : public Pass {
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MyPass() : Pass("my_cmd", "just a simple test") { }
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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log("Arguments to my_cmd:\n");
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for (auto &arg : args)
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log(" %s\n", arg.c_str());
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log("Modules in current design:\n");
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for (auto mod : design->modules())
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log(" %s (%d wires, %d cells)\n", log_id(mod),
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GetSize(mod->wires()), GetSize(mod->cells()));
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}
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} MyPass;
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Creating a plugin
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~~~~~~~~~~~~~~~~~
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Yosys can be extended by adding additional C++ code to the Yosys code base, or
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by loading plugins into Yosys.
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Use the following command to compile a Yosys plugin:
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.. code::
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yosys-config --exec --cxx --cxxflags --ldflags \
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-o my_cmd.so -shared my_cmd.cc --ldlibs
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Or shorter:
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.. code::
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yosys-config --build my_cmd.so my_cmd.cc
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Load the plugin using the yosys ``-m`` option:
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.. code::
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yosys -m ./my_cmd.so -p 'my_cmd foo bar'
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