mirror of https://github.com/YosysHQ/yosys.git
143 lines
3.9 KiB
C++
143 lines
3.9 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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#include "passes/pmgen/xilinx_dsp_pm.h"
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void pack_xilinx_dsp(xilinx_dsp_pm &pm)
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{
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auto &st = pm.st_xilinx_dsp;
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#if 1
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log("\n");
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log("ffA: %s\n", log_id(st.ffA, "--"));
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log("ffB: %s\n", log_id(st.ffB, "--"));
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log("dsp: %s\n", log_id(st.dsp, "--"));
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log("ffP: %s\n", log_id(st.ffP, "--"));
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log("muxP: %s\n", log_id(st.muxP, "--"));
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log("P_WIDTH: %d\n", st.P_WIDTH);
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#endif
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log("Analysing %s.%s for Xilinx DSP register packing.\n", log_id(pm.module), log_id(st.dsp));
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Cell *cell = st.dsp;
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log_assert(cell);
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if (st.clock != SigBit())
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{
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cell->setPort("\\CLK", st.clock);
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if (st.ffA) {
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SigSpec A = cell->getPort("\\A");
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SigSpec D = st.ffA->getPort("\\D");
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SigSpec Q = st.ffA->getPort("\\Q");
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A.replace(Q, D);
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cell->setPort("\\A", A);
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cell->setParam("\\AREG", State::S1);
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if (st.ffA->type == "$dff")
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cell->setPort("\\CEA2", State::S1);
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else if (st.ffA->type == "$dffe")
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cell->setPort("\\CEA2", st.ffA->getPort("\\EN"));
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else log_abort();
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}
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if (st.ffB) {
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SigSpec B = cell->getPort("\\B");
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SigSpec D = st.ffB->getPort("\\D");
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SigSpec Q = st.ffB->getPort("\\Q");
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B.replace(Q, D);
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cell->setPort("\\B", B);
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cell->setParam("\\BREG", State::S1);
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if (st.ffB->type == "$dff")
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cell->setPort("\\CEB2", State::S1);
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else if (st.ffB->type == "$dffe")
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cell->setPort("\\CEB2", st.ffB->getPort("\\EN"));
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else log_abort();
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}
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if (st.ffP) {
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SigSpec P = cell->getPort("\\P");
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SigSpec Q = st.ffP->getPort("\\Q");
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P.replace(Q, P.extract(0, GetSize(Q)));
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cell->setPort("\\P", Q);
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cell->setParam("\\PREG", State::S1);
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if (st.ffP->type == "$dff")
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cell->setPort("\\CEP", State::S1);
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else if (st.ffP->type == "$dffe")
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cell->setPort("\\CEP", st.ffP->getPort("\\EN"));
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else log_abort();
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}
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log(" clock: %s (%s)", log_signal(st.clock), "posedge");
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if (st.ffA)
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log(" ffA:%s", log_id(st.ffA));
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if (st.ffB)
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log(" ffB:%s", log_id(st.ffB));
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if (st.ffP)
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log(" ffY:%s", log_id(st.ffP));
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log("\n");
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}
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pm.autoremove(st.ffA);
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pm.autoremove(st.ffB);
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pm.autoremove(st.ffP);
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pm.autoremove(st.muxP);
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pm.blacklist(cell);
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}
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struct Ice40DspPass : public Pass {
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Ice40DspPass() : Pass("xilinx_dsp", "Xilinx: pack DSP registers") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" xilinx_dsp [options] [selection]\n");
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log("\n");
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log("Pack registers into Xilinx DSPs\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing XILINX_DSP pass (pack DSPs).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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// if (args[argidx] == "-singleton") {
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// singleton_mode = true;
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// continue;
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// }
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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xilinx_dsp_pm(module, module->selected_cells()).run_xilinx_dsp(pack_xilinx_dsp);
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}
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} Ice40DspPass;
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PRIVATE_NAMESPACE_END
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