mirror of https://github.com/YosysHQ/yosys.git
22 lines
361 B
Plaintext
22 lines
361 B
Plaintext
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read_verilog -formal <<EOT
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module gate(input clk, output [1:0] o);
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assign o = 1'bx;
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endmodule
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EOT
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proc
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## Equivalence checking
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read_verilog -formal <<EOT
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module gold(input clk, output [1:0] o);
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assign o = 2'bxx;
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endmodule
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EOT
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proc
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports -enable_undef miter
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