mirror of https://github.com/YosysHQ/yosys.git
632 lines
16 KiB
Verilog
632 lines
16 KiB
Verilog
// The core logic primitive of the Cyclone V/10GX is the Adaptive Logic Module
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// (ALM). Each ALM is made up of an 8-input, 2-output look-up table, covered
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// in this file, connected to combinational outputs, a carry chain, and four
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// D flip-flops (which are covered as MISTRAL_FF in dff_sim.v).
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//
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// The ALM is vertically symmetric, so I find it helps to think in terms of
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// half-ALMs, as that's predominantly the unit that synth_intel_alm uses.
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//
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// ALMs are quite flexible, having multiple modes.
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//
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// Normal (combinational) mode
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// ---------------------------
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// The ALM can implement:
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// - a single 6-input function (with the other inputs usable for flip-flop access)
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// - two 5-input functions that share two inputs
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// - a 5-input and a 4-input function that share one input
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// - a 5-input and a 3-or-less-input function that share no inputs
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// - two 4-or-less-input functions that share no inputs
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//
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// Normal-mode functions are represented as MISTRAL_ALUTN cells with N inputs.
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// It would be possible to represent a normal mode function as a single cell -
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// the vendor cyclone{v,10gx}_lcell_comb cell does exactly that - but I felt
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// it was more user-friendly to print out the specific function sizes
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// separately.
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//
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// With the exception of MISTRAL_ALUT6, you can think of two normal-mode cells
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// fitting inside a single ALM.
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//
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// Extended (7-input) mode
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// -----------------------
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// The ALM can also fit a 7-input function made of two 5-input functions that
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// share four inputs, multiplexed by another input.
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//
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// Because this can't accept arbitrary 7-input functions, Yosys can't handle
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// it, so it doesn't have a cell, but I would likely call it MISTRAL_ALUT7(E?)
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// if it did, and it would take up a full ALM.
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//
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// It might be possible to add an extraction pass to examine all ALUT5 cells
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// that feed into ALUT3 cells to see if they can be combined into an extended
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// ALM, but I don't think it will be worth it.
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//
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// Arithmetic mode
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// ---------------
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// In arithmetic mode, each half-ALM uses its carry chain to perform fast addition
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// of two four-input functions that share three inputs. Oddly, the result of
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// one of the functions is inverted before being added (you can see this as
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// the dot on a full-adder input of Figure 1-8 in the Handbook).
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//
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// The cell for an arithmetic-mode half-ALM is MISTRAL_ALM_ARITH. One idea
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// I've had (or rather was suggested by mwk) is that functions that feed into
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// arithmetic-mode cells could be packed directly into the arithmetic-mode
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// cell as a function, which reduces the number of ALMs needed.
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//
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// Shared arithmetic mode
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// ----------------------
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// Shared arithmetic mode looks a lot like arithmetic mode, but here the
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// output of every other four-input function goes to the input of the adder
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// the next bit along. What this means is that adding three bits together can
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// be done in an ALM, because functions can be used to implement addition that
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// then feeds into the carry chain. This means that three bits can be added per
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// ALM, as opposed to two in the arithmetic mode.
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//
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// Shared arithmetic mode doesn't currently have a cell, but I intend to add
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// it as MISTRAL_ALM_SHARED, and have it occupy a full ALM. Because it adds
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// three bits per cell, it makes addition shorter and use less ALMs, but
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// I don't know enough to tell whether it's more efficient to use shared
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// arithmetic mode to shorten the carry chain, or plain arithmetic mode with
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// the functions packed in.
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`default_nettype none
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// Cyclone V LUT output timings (picoseconds):
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//
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// CARRY A B C D E F G
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// COMBOUT - 605 583 510 512 - 97 400 (LUT6)
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// COMBOUT - 602 583 457 510 302 93 483 (LUT7)
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// SUMOUT 368 1342 1323 887 927 - 785 -
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// CARRYOUT 71 1082 1062 866 813 - 1198 -
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// Arria V LUT output timings (picoseconds):
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//
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// CARRY A B C D E F G
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// COMBOUT - 387 375 316 317 - 76 319 (LUT6)
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// COMBOUT - 387 375 316 317 218 76 319 (LUT7)
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// SUMOUT 249 744 732 562 576 - 511 -
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// CARRYOUT 19 629 623 530 514 - 696 -
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(* abc9_lut=2, lib_whitebox *)
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module MISTRAL_ALUT6(input A, B, C, D, E, F, output Q);
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parameter [63:0] LUT = 64'h0000_0000_0000_0000;
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`ifdef cyclonev
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specify
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(A => Q) = 605;
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(B => Q) = 583;
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(C => Q) = 510;
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(D => Q) = 512;
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(E => Q) = 400;
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(F => Q) = 97;
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endspecify
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`endif
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`ifdef arriav
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specify
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(A => Q) = 387;
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(B => Q) = 375;
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(C => Q) = 316;
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(D => Q) = 317;
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(E => Q) = 319;
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(F => Q) = 76;
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endspecify
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`endif
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`ifdef cyclone10gx
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specify
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(A => Q) = 275;
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(B => Q) = 272;
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(C => Q) = 175;
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(D => Q) = 165;
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(E => Q) = 162;
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(F => Q) = 53;
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endspecify
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`endif
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assign Q = LUT >> {F, E, D, C, B, A};
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endmodule
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(* abc9_lut=1, lib_whitebox *)
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module MISTRAL_ALUT5(input A, B, C, D, E, output Q);
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parameter [31:0] LUT = 32'h0000_0000;
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`ifdef cyclonev
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specify
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(A => Q) = 583;
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(B => Q) = 510;
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(C => Q) = 512;
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(D => Q) = 400;
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(E => Q) = 97;
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endspecify
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`endif
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`ifdef arriav
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specify
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(A => Q) = 375;
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(B => Q) = 316;
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(C => Q) = 317;
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(D => Q) = 319;
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(E => Q) = 76;
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endspecify
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`endif
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`ifdef cyclone10gx
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specify
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(A => Q) = 272;
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(B => Q) = 175;
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(C => Q) = 165;
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(D => Q) = 162;
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(E => Q) = 53;
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endspecify
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`endif
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assign Q = LUT >> {E, D, C, B, A};
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endmodule
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(* abc9_lut=1, lib_whitebox *)
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module MISTRAL_ALUT4(input A, B, C, D, output Q);
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parameter [15:0] LUT = 16'h0000;
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`ifdef cyclonev
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specify
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(A => Q) = 510;
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(B => Q) = 512;
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(C => Q) = 400;
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(D => Q) = 97;
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endspecify
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`endif
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`ifdef arriav
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specify
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(A => Q) = 316;
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(B => Q) = 317;
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(C => Q) = 319;
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(D => Q) = 76;
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endspecify
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`endif
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`ifdef cyclone10gx
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specify
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(A => Q) = 175;
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(B => Q) = 165;
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(C => Q) = 162;
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(D => Q) = 53;
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endspecify
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`endif
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assign Q = LUT >> {D, C, B, A};
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endmodule
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(* abc9_lut=1, lib_whitebox *)
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module MISTRAL_ALUT3(input A, B, C, output Q);
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parameter [7:0] LUT = 8'h00;
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`ifdef cyclonev
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specify
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(A => Q) = 510;
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(B => Q) = 400;
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(C => Q) = 97;
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endspecify
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`endif
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`ifdef arriav
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specify
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(A => Q) = 316;
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(B => Q) = 317;
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(C => Q) = 76;
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endspecify
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`endif
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`ifdef cyclone10gx
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specify
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(A => Q) = 165;
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(B => Q) = 162;
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(C => Q) = 53;
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endspecify
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`endif
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assign Q = LUT >> {C, B, A};
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endmodule
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(* abc9_lut=1, lib_whitebox *)
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module MISTRAL_ALUT2(input A, B, output Q);
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parameter [3:0] LUT = 4'h0;
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`ifdef cyclonev
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specify
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(A => Q) = 400;
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(B => Q) = 97;
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endspecify
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`endif
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`ifdef arriav
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specify
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(A => Q) = 316;
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(B => Q) = 76;
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endspecify
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`endif
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`ifdef cyclone10gx
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specify
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(A => Q) = 162;
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(B => Q) = 53;
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endspecify
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`endif
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assign Q = LUT >> {B, A};
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endmodule
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(* abc9_lut=1, lib_whitebox *)
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module MISTRAL_NOT(input A, output Q);
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`ifdef cyclonev
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specify
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(A => Q) = 97;
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endspecify
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`endif
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`ifdef arriav
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specify
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(A => Q) = 76;
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endspecify
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`endif
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`ifdef cyclone10gx
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specify
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(A => Q) = 53;
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endspecify
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`endif
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assign Q = ~A;
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endmodule
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(* abc9_box, lib_whitebox *)
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module MISTRAL_ALUT_ARITH(input A, B, C, D0, D1, (* abc9_carry *) input CI, output SO, (* abc9_carry *) output CO);
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parameter LUT0 = 16'h0000;
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parameter LUT1 = 16'h0000;
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`ifdef cyclonev
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specify
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(A => SO) = 1342;
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(B => SO) = 1323;
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(C => SO) = 927;
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(D0 => SO) = 887;
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(D1 => SO) = 785;
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(CI => SO) = 368;
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(A => CO) = 1082;
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(B => CO) = 1062;
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(C => CO) = 813;
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(D0 => CO) = 866;
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(D1 => CO) = 1198;
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(CI => CO) = 36; // Divided by 2 to account for there being two ALUT_ARITHs in an ALM)
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endspecify
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`endif
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`ifdef arriav
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specify
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(A => SO) = 744;
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(B => SO) = 732;
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(C => SO) = 562;
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(D0 => SO) = 576;
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(D1 => SO) = 511;
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(CI => SO) = 249;
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(A => CO) = 629;
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(B => CO) = 623;
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(C => CO) = 530;
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(D0 => CO) = 514;
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(D1 => CO) = 696;
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(CI => CO) = 10; // Divided by 2 to account for there being two ALUT_ARITHs in an ALM)
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endspecify
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`endif
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`ifdef cyclone10gx
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specify
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(A => SO) = 644;
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(B => SO) = 477;
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(C => SO) = 416;
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(D0 => SO) = 380;
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(D1 => SO) = 431;
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(CI => SO) = 276;
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(A => CO) = 525;
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(B => CO) = 433;
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(C => CO) = 712;
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(D0 => CO) = 653;
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(D1 => CO) = 593;
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(CI => CO) = 16;
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endspecify
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`endif
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wire q0, q1;
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assign q0 = LUT0 >> {D0, C, B, A};
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assign q1 = LUT1 >> {D1, C, B, A};
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assign {CO, SO} = q0 + !q1 + CI;
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endmodule
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/*
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// A, B, C0, C1, E0, E1, F0, F1: data inputs
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// CARRYIN: carry input
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// SHAREIN: shared-arithmetic input
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// CLK0, CLK1, CLK2: clock inputs
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//
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// COMB0, COMB1: combinational outputs
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// FF0, FF1, FF2, FF3: DFF outputs
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// SUM0, SUM1: adder outputs
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// CARRYOUT: carry output
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// SHAREOUT: shared-arithmetic output
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module MISTRAL_ALM(
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input A, B, C0, C1, E0, E1, F0, F1, CARRYIN, SHAREIN, // LUT path
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input CLK0, CLK1, CLK2, AC0, AC1, // FF path
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output COMB0, COMB1, SUM0, SUM1, CARRYOUT, SHAREOUT,
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output FF0, FF1, FF2, FF3
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);
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parameter LUT0 = 16'b0000;
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parameter LUT1 = 16'b0000;
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parameter LUT2 = 16'b0000;
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parameter LUT3 = 16'b0000;
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parameter INIT0 = 1'b0;
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parameter INIT1 = 1'b0;
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parameter INIT2 = 1'b0;
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parameter INIT3 = 1'b0;
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parameter C0_MUX = "C0";
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parameter C1_MUX = "C1";
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parameter F0_MUX = "VCC";
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parameter F1_MUX = "GND";
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parameter FEEDBACK0 = "FF0";
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parameter FEEDBACK1 = "FF2";
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parameter ADD_MUX = "LUT";
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parameter DFF01_DATA_MUX = "COMB";
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parameter DFF23_DATA_MUX = "COMB";
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parameter DFF0_CLK = "CLK0";
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parameter DFF1_CLK = "CLK0";
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parameter DFF2_CLK = "CLK0";
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parameter DFF3_CLK = "CLK0";
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parameter DFF0_AC = "AC0";
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parameter DFF1_AC = "AC0";
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parameter DFF2_AC = "AC0";
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parameter DFF3_AC = "AC0";
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// Feedback muxes from the flip-flop outputs.
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wire ff_feedback_mux0, ff_feedback_mux1;
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// C-input muxes which can be set to also use the F-input.
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wire c0_input_mux, c1_input_mux;
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// F-input muxes which can be set to a constant to allow LUT5 use.
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wire f0_input_mux, f1_input_mux;
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// Adder input muxes to select between shared-arithmetic mode and arithmetic mode.
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wire add0_input_mux, add1_input_mux;
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// Combinational-output muxes for LUT #1 and LUT #3
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wire lut1_comb_mux, lut3_comb_mux;
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// Sum-output muxes for LUT #1 and LUT #3
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wire lut1_sum_mux, lut3_sum_mux;
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// DFF data-input muxes
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wire dff01_data_mux, dff23_data_mux;
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// DFF clock selectors
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wire dff0_clk, dff1_clk, dff2_clk, dff3_clk;
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// DFF asynchronous-clear selectors
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wire dff0_ac, dff1_ac, dff2_ac, dff3_ac;
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// LUT, DFF and adder output wires for routing.
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wire lut0_out, lut1a_out, lut1b_out, lut2_out, lut3a_out, lut3b_out;
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wire dff0_out, dff1_out, dff2_out, dff3_out;
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wire add0_sum, add1_sum, add0_carry, add1_carry;
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generate
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if (FEEDBACK0 === "FF0")
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assign ff_feedback_mux0 = dff0_out;
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else if (FEEDBACK0 === "FF1")
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assign ff_feedback_mux0 = dff1_out;
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else
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$error("Invalid FEEDBACK0 setting!");
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if (FEEDBACK1 == "FF2")
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assign ff_feedback_mux1 = dff2_out;
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else if (FEEDBACK1 == "FF3")
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assign ff_feedback_mux1 = dff3_out;
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else
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$error("Invalid FEEDBACK1 setting!");
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if (C0_MUX === "C0")
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assign c0_input_mux = C0;
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else if (C0_MUX === "F1")
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assign c0_input_mux = F1;
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else if (C0_MUX === "FEEDBACK1")
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assign c0_input_mux = ff_feedback_mux1;
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else
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$error("Invalid C0_MUX setting!");
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if (C1_MUX === "C1")
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assign c1_input_mux = C1;
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else if (C1_MUX === "F0")
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assign c1_input_mux = F0;
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else if (C1_MUX === "FEEDBACK0")
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assign c1_input_mux = ff_feedback_mux0;
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else
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$error("Invalid C1_MUX setting!");
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// F0 == VCC is LUT5
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// F0 == F0 is LUT6
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// F0 == FEEDBACK is unknown
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if (F0_MUX === "VCC")
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assign f0_input_mux = 1'b1;
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else if (F0_MUX === "F0")
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assign f0_input_mux = F0;
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else if (F0_MUX === "FEEDBACK0")
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assign f0_input_mux = ff_feedback_mux0;
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else
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$error("Invalid F0_MUX setting!");
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// F1 == GND is LUT5
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// F1 == F1 is LUT6
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// F1 == FEEDBACK is unknown
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if (F1_MUX === "GND")
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assign f1_input_mux = 1'b0;
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else if (F1_MUX === "F1")
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assign f1_input_mux = F1;
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else if (F1_MUX === "FEEDBACK1")
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assign f1_input_mux = ff_feedback_mux1;
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else
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$error("Invalid F1_MUX setting!");
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if (ADD_MUX === "LUT") begin
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assign add0_input_mux = ~lut1_sum_mux;
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assign add1_input_mux = ~lut3_sum_mux;
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end else if (ADD_MUX === "SHARE") begin
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assign add0_input_mux = SHAREIN;
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assign add1_input_mux = lut1_comb_mux;
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end else
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$error("Invalid ADD_MUX setting!");
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if (DFF01_DATA_MUX === "COMB")
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assign dff01_data_mux = COMB0;
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else if (DFF01_DATA_MUX === "SUM")
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assign dff01_data_mux = SUM0;
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else
|
|
$error("Invalid DFF01_DATA_MUX setting!");
|
|
|
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if (DFF23_DATA_MUX === "COMB")
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assign dff23_data_mux = COMB0;
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else if (DFF23_DATA_MUX === "SUM")
|
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assign dff23_data_mux = SUM0;
|
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else
|
|
$error("Invalid DFF23_DATA_MUX setting!");
|
|
|
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if (DFF0_CLK === "CLK0")
|
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assign dff0_clk = CLK0;
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else if (DFF0_CLK === "CLK1")
|
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assign dff0_clk = CLK1;
|
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else if (DFF0_CLK === "CLK2")
|
|
assign dff0_clk = CLK2;
|
|
else
|
|
$error("Invalid DFF0_CLK setting!");
|
|
|
|
if (DFF1_CLK === "CLK0")
|
|
assign dff1_clk = CLK0;
|
|
else if (DFF1_CLK === "CLK1")
|
|
assign dff1_clk = CLK1;
|
|
else if (DFF1_CLK === "CLK2")
|
|
assign dff1_clk = CLK2;
|
|
else
|
|
$error("Invalid DFF1_CLK setting!");
|
|
|
|
if (DFF2_CLK === "CLK0")
|
|
assign dff2_clk = CLK0;
|
|
else if (DFF2_CLK === "CLK1")
|
|
assign dff2_clk = CLK1;
|
|
else if (DFF2_CLK === "CLK2")
|
|
assign dff2_clk = CLK2;
|
|
else
|
|
$error("Invalid DFF2_CLK setting!");
|
|
|
|
if (DFF3_CLK === "CLK0")
|
|
assign dff3_clk = CLK0;
|
|
else if (DFF3_CLK === "CLK1")
|
|
assign dff3_clk = CLK1;
|
|
else if (DFF3_CLK === "CLK2")
|
|
assign dff3_clk = CLK2;
|
|
else
|
|
$error("Invalid DFF3_CLK setting!");
|
|
|
|
if (DFF0_AC === "AC0")
|
|
assign dff0_ac = AC0;
|
|
else if (DFF0_AC === "AC1")
|
|
assign dff0_ac = AC1;
|
|
else
|
|
$error("Invalid DFF0_AC setting!");
|
|
|
|
if (DFF1_AC === "AC0")
|
|
assign dff1_ac = AC0;
|
|
else if (DFF1_AC === "AC1")
|
|
assign dff1_ac = AC1;
|
|
else
|
|
$error("Invalid DFF1_AC setting!");
|
|
|
|
if (DFF2_AC === "AC0")
|
|
assign dff2_ac = AC0;
|
|
else if (DFF2_AC === "AC1")
|
|
assign dff2_ac = AC1;
|
|
else
|
|
$error("Invalid DFF2_AC setting!");
|
|
|
|
if (DFF3_AC === "AC0")
|
|
assign dff3_ac = AC0;
|
|
else if (DFF3_AC === "AC1")
|
|
assign dff3_ac = AC1;
|
|
else
|
|
$error("Invalid DFF3_AC setting!");
|
|
|
|
endgenerate
|
|
|
|
// F0 on the Quartus diagram
|
|
MISTRAL_ALUT4 #(.LUT(LUT0)) lut0 (.A(A), .B(B), .C(C0), .D(c1_input_mux), .Q(lut0_out));
|
|
|
|
// F2 on the Quartus diagram
|
|
MISTRAL_ALUT4 #(.LUT(LUT1)) lut1_comb (.A(A), .B(B), .C(C0), .D(c1_input_mux), .Q(lut1_comb_mux));
|
|
MISTRAL_ALUT4 #(.LUT(LUT1)) lut1_sum (.A(A), .B(B), .C(C0), .D(E0), .Q(lut1_sum_mux));
|
|
|
|
// F1 on the Quartus diagram
|
|
MISTRAL_ALUT4 #(.LUT(LUT2)) lut2 (.A(A), .B(B), .C(C1), .D(c0_input_mux), .Q(lut2_out));
|
|
|
|
// F3 on the Quartus diagram
|
|
MISTRAL_ALUT4 #(.LUT(LUT3)) lut3_comb (.A(A), .B(B), .C(C1), .D(c0_input_mux), .Q(lut3_comb_mux));
|
|
MISTRAL_ALUT4 #(.LUT(LUT3)) lut3_sum (.A(A), .B(B), .C(C1), .D(E1), .Q(lut3_sum_mux));
|
|
|
|
MISTRAL_FF #(.INIT(INIT0)) dff0 (.D(dff01_data_mux), .CLK(dff0_clk), .ACn(dff0_ac), .Q(dff0_out));
|
|
MISTRAL_FF #(.INIT(INIT1)) dff1 (.D(dff01_data_mux), .CLK(dff1_clk), .ACn(dff1_ac), .Q(dff1_out));
|
|
MISTRAL_FF #(.INIT(INIT2)) dff2 (.D(dff23_data_mux), .CLK(dff2_clk), .ACn(dff2_ac), .Q(dff2_out));
|
|
MISTRAL_FF #(.INIT(INIT3)) dff3 (.D(dff23_data_mux), .CLK(dff3_clk), .ACn(dff3_ac), .Q(dff3_out));
|
|
|
|
// Adders
|
|
assign {add0_carry, add0_sum} = CARRYIN + lut0_out + lut1_sum_mux;
|
|
assign {add1_carry, add1_sum} = add0_carry + lut2_out + lut3_sum_mux;
|
|
|
|
// COMBOUT outputs on the Quartus diagram
|
|
assign COMB0 = E0 ? (f0_input_mux ? lut3_comb_mux : lut1_comb_mux)
|
|
: (f0_input_mux ? lut2_out : lut0_out);
|
|
|
|
assign COMB1 = E1 ? (f1_input_mux ? lut3_comb_mux : lut1_comb_mux)
|
|
: (f1_input_mux ? lut2_out : lut0_out);
|
|
|
|
// SUMOUT output on the Quartus diagram
|
|
assign SUM0 = add0_sum;
|
|
assign SUM1 = add1_sum;
|
|
|
|
// COUT output on the Quartus diagram
|
|
assign CARRYOUT = add1_carry;
|
|
|
|
// SHAREOUT output on the Quartus diagram
|
|
assign SHAREOUT = lut3_comb_mux;
|
|
|
|
// REGOUT outputs on the Quartus diagram
|
|
assign FF0 = dff0_out;
|
|
assign FF1 = dff1_out;
|
|
assign FF2 = dff2_out;
|
|
assign FF3 = dff3_out;
|
|
|
|
endmodule
|
|
*/
|