mirror of https://github.com/YosysHQ/yosys.git
40 lines
846 B
Verilog
40 lines
846 B
Verilog
module test(input [31:0] in, input [4:0] select, output reg out);
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always @( in or select)
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case (select)
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0: out = in[0];
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1: out = in[1];
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2: out = in[2];
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3: out = in[3];
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4: out = in[4];
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5: out = in[5];
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6: out = in[6];
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7: out = in[7];
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8: out = in[8];
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9: out = in[9];
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10: out = in[10];
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11: out = in[11];
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12: out = in[12];
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13: out = in[13];
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14: out = in[14];
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15: out = in[15];
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16: out = in[16];
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17: out = in[17];
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18: out = in[18];
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19: out = in[19];
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20: out = in[20];
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21: out = in[21];
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22: out = in[22];
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23: out = in[23];
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24: out = in[24];
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25: out = in[25];
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26: out = in[26];
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27: out = in[27];
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28: out = in[28];
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29: out = in[29];
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30: out = in[30];
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31: out = in[31];
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endcase
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endmodule
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