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aiger
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Merge pull request #1238 from mmicko/vsbuild_fix
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2019-08-02 17:07:39 +02:00 |
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blif
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Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
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2019-08-06 04:47:55 +02:00 |
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btor
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Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
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2019-08-06 04:47:55 +02:00 |
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edif
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Add "whitebox" attribute, add "read_verilog -wb"
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2019-04-18 17:45:47 +02:00 |
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firrtl
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Fix static shift operands, neg result type, minor formatting
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2019-05-21 13:04:56 -07:00 |
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ilang
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Allow attributes on individual switch cases in RTLIL.
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2019-07-08 11:34:58 +00:00 |
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intersynth
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Add "whitebox" attribute, add "read_verilog -wb"
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2019-04-18 17:45:47 +02:00 |
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json
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Fix json formatting
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2019-06-21 20:01:40 +02:00 |
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protobuf
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Support filename rewrite in backends
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2019-06-18 14:39:52 -07:00 |
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simplec
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Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
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2019-08-06 04:47:55 +02:00 |
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smt2
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Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
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2019-08-06 04:47:55 +02:00 |
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smv
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Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
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2019-08-06 04:47:55 +02:00 |
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spice
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Add "whitebox" attribute, add "read_verilog -wb"
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2019-04-18 17:45:47 +02:00 |
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table
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Add "whitebox" attribute, add "read_verilog -wb"
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2019-04-18 17:45:47 +02:00 |
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verilog
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Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
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2019-08-06 04:47:55 +02:00 |
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