Eddie Hung 1f722b3500 Remove signed from ports in +/xilinx/dsp_map.v		2019-08-08 16:33:20 -07:00
..
achronix	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
anlogic	anlogic : Fix alu mapping	2019-08-03 14:47:33 +02:00
common	Merge remote-tracking branch 'origin/master' into xc7dsp	2019-08-07 13:44:08 -07:00
coolrunner2	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
easic	Fix typographical and grammatical errors and inconsistencies.	2019-01-02 13:12:17 +00:00
ecp5	ecp5: Replace '-dsp' with inverse logic '-nodsp' to match synth_xilinx	2019-08-08 15:18:59 +01:00
gowin	Fix formatting for msys2 mingw build using GetSize	2019-08-01 17:27:34 +02:00
greenpak4	techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module	2019-02-26 09:40:46 -08:00
ice40	Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing	2019-08-08 12:56:05 -07:00
intel	Merge branch 'ZirconiumX-synth_intel_m9k'	2019-07-25 17:23:48 +02:00
sf2	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
xilinx	Remove signed from ports in +/xilinx/dsp_map.v	2019-08-08 16:33:20 -07:00
.gitignore	added .gitignore files	2013-01-05 11:19:11 +01:00