yosys/backends/verilog
Clifford Wolf 33738c1745 Fix handling of partial init attributes in write_verilog, fixes #997
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-07 19:55:36 +02:00
..
Makefile.inc initial import 2013-01-05 11:13:26 +01:00
verilog_backend.cc Fix handling of partial init attributes in write_verilog, fixes #997 2019-05-07 19:55:36 +02:00