mirror of https://github.com/YosysHQ/yosys.git
424 lines
13 KiB
C++
424 lines
13 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/log.h"
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#include "kernel/mem.h"
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#include <sstream>
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#include <set>
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#include <stdlib.h>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct MemoryMapWorker
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{
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bool attr_icase = false;
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dict<RTLIL::IdString, std::vector<RTLIL::Const>> attributes;
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RTLIL::Design *design;
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RTLIL::Module *module;
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std::map<std::pair<RTLIL::SigSpec, RTLIL::SigSpec>, RTLIL::SigBit> decoder_cache;
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MemoryMapWorker(RTLIL::Design *design, RTLIL::Module *module) : design(design), module(module) {}
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std::string map_case(std::string value) const
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{
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if (attr_icase) {
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for (char &c : value)
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c = tolower(c);
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}
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return value;
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}
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RTLIL::Const map_case(RTLIL::Const value) const
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{
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if (value.flags & RTLIL::CONST_FLAG_STRING)
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return map_case(value.decode_string());
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return value;
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}
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std::string genid(RTLIL::IdString name, std::string token1 = "", int i = -1, std::string token2 = "", int j = -1, std::string token3 = "", int k = -1, std::string token4 = "")
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{
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std::stringstream sstr;
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sstr << "$memory" << name.str() << token1;
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if (i >= 0)
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sstr << "[" << i << "]";
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sstr << token2;
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if (j >= 0)
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sstr << "[" << j << "]";
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sstr << token3;
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if (k >= 0)
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sstr << "[" << k << "]";
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sstr << token4 << "$" << (autoidx++);
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return sstr.str();
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}
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RTLIL::Wire *addr_decode(RTLIL::SigSpec addr_sig, RTLIL::SigSpec addr_val)
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{
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std::pair<RTLIL::SigSpec, RTLIL::SigSpec> key(addr_sig, addr_val);
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log_assert(GetSize(addr_sig) == GetSize(addr_val));
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if (decoder_cache.count(key) == 0) {
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if (GetSize(addr_sig) < 2) {
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decoder_cache[key] = module->Eq(NEW_ID, addr_sig, addr_val);
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} else {
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int split_at = GetSize(addr_sig) / 2;
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RTLIL::SigBit left_eq = addr_decode(addr_sig.extract(0, split_at), addr_val.extract(0, split_at));
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RTLIL::SigBit right_eq = addr_decode(addr_sig.extract(split_at, GetSize(addr_sig) - split_at), addr_val.extract(split_at, GetSize(addr_val) - split_at));
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decoder_cache[key] = module->And(NEW_ID, left_eq, right_eq);
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}
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}
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RTLIL::SigBit bit = decoder_cache.at(key);
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log_assert(bit.wire != nullptr && GetSize(bit.wire) == 1);
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return bit.wire;
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}
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void handle_memory(Mem &mem)
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{
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std::set<int> static_ports;
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std::map<int, RTLIL::SigSpec> static_cells_map;
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SigSpec init_data = mem.get_init_data();
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// delete unused memory cell
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if (mem.rd_ports.empty()) {
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mem.remove();
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return;
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}
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// check if attributes allow us to infer FFRAM for this memory
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for (const auto &attr : attributes) {
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if (mem.attributes.count(attr.first)) {
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const auto &cell_attr = mem.attributes[attr.first];
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if (attr.second.empty()) {
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log("Not mapping memory %s in module %s (attribute %s is set).\n",
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mem.memid.c_str(), module->name.c_str(), attr.first.c_str());
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return;
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}
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bool found = false;
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for (auto &value : attr.second) {
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if (map_case(cell_attr) == map_case(value)) {
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found = true;
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break;
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}
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}
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if (!found) {
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if (cell_attr.flags & RTLIL::CONST_FLAG_STRING) {
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log("Not mapping memory %s in module %s (attribute %s is set to \"%s\").\n",
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mem.memid.c_str(), module->name.c_str(), attr.first.c_str(), cell_attr.decode_string().c_str());
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} else {
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log("Not mapping memory %s in module %s (attribute %s is set to %d).\n",
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mem.memid.c_str(), module->name.c_str(), attr.first.c_str(), cell_attr.as_int());
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}
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return;
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}
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}
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}
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// all write ports must share the same clock
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RTLIL::SigSpec refclock;
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bool refclock_pol = false;
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for (int i = 0; i < GetSize(mem.wr_ports); i++) {
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auto &port = mem.wr_ports[i];
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if (port.en.is_fully_const() && !port.en.as_bool()) {
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static_ports.insert(i);
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continue;
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}
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if (!port.clk_enable) {
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if (port.addr.is_fully_const()) {
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// FIXME: Actually we should check for port.en.is_fully_const() also and
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// create a $adff cell with this ports port.en input as reset pin when port.en
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// is not a simple static 1.
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static_cells_map[port.addr.as_int() - mem.start_offset] = port.data;
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static_ports.insert(i);
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continue;
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}
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log("Not mapping memory %s in module %s (write port %d has no clock).\n",
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mem.memid.c_str(), module->name.c_str(), i);
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return;
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}
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if (refclock.size() == 0) {
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refclock = port.clk;
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refclock_pol = port.clk_polarity;
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}
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if (port.clk != refclock || port.clk_polarity != refclock_pol) {
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log("Not mapping memory %s in module %s (write clock %d is incompatible with other clocks).\n",
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mem.memid.c_str(), module->name.c_str(), i);
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return;
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}
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}
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log("Mapping memory %s in module %s:\n", mem.memid.c_str(), module->name.c_str());
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std::vector<RTLIL::SigSpec> data_reg_in;
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std::vector<RTLIL::SigSpec> data_reg_out;
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int count_static = 0;
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for (int i = 0; i < mem.size; i++)
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{
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if (static_cells_map.count(i) > 0)
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{
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data_reg_in.push_back(RTLIL::SigSpec(RTLIL::State::Sz, mem.width));
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data_reg_out.push_back(static_cells_map[i]);
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count_static++;
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}
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else
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{
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RTLIL::Cell *c = module->addCell(genid(mem.memid, "", i), ID($dff));
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c->parameters[ID::WIDTH] = mem.width;
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if (GetSize(refclock) != 0) {
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c->parameters[ID::CLK_POLARITY] = RTLIL::Const(refclock_pol);
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c->setPort(ID::CLK, refclock);
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} else {
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c->parameters[ID::CLK_POLARITY] = RTLIL::Const(RTLIL::State::S1);
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c->setPort(ID::CLK, RTLIL::SigSpec(RTLIL::State::S0));
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}
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RTLIL::Wire *w_in = module->addWire(genid(mem.memid, "", i, "$d"), mem.width);
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data_reg_in.push_back(RTLIL::SigSpec(w_in));
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c->setPort(ID::D, data_reg_in.back());
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std::string w_out_name = stringf("%s[%d]", mem.memid.c_str(), i);
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if (module->wires_.count(w_out_name) > 0)
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w_out_name = genid(mem.memid, "", i, "$q");
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RTLIL::Wire *w_out = module->addWire(w_out_name, mem.width);
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SigSpec w_init = init_data.extract(i*mem.width, mem.width);
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if (!w_init.is_fully_undef())
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w_out->attributes[ID::init] = w_init.as_const();
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data_reg_out.push_back(RTLIL::SigSpec(w_out));
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c->setPort(ID::Q, data_reg_out.back());
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}
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}
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log(" created %d $dff cells and %d static cells of width %d.\n", mem.size-count_static, count_static, mem.width);
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int count_dff = 0, count_mux = 0, count_wrmux = 0;
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int abits = ceil_log2(mem.size);
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for (int i = 0; i < GetSize(mem.rd_ports); i++)
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{
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auto &port = mem.rd_ports[i];
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if (mem.extract_rdff(i))
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count_dff++;
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RTLIL::SigSpec rd_addr = port.addr;
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rd_addr.extend_u0(abits, false);
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if (mem.start_offset)
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rd_addr = module->Sub(NEW_ID, rd_addr, SigSpec(mem.start_offset, abits));
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std::vector<RTLIL::SigSpec> rd_signals;
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rd_signals.push_back(port.data);
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for (int j = 0; j < abits; j++)
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{
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std::vector<RTLIL::SigSpec> next_rd_signals;
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for (size_t k = 0; k < rd_signals.size(); k++)
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{
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RTLIL::Cell *c = module->addCell(genid(mem.memid, "$rdmux", i, "", j, "", k), ID($mux));
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c->parameters[ID::WIDTH] = mem.width;
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c->setPort(ID::Y, rd_signals[k]);
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c->setPort(ID::S, rd_addr.extract(abits-j-1, 1));
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count_mux++;
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c->setPort(ID::A, module->addWire(genid(mem.memid, "$rdmux", i, "", j, "", k, "$a"), mem.width));
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c->setPort(ID::B, module->addWire(genid(mem.memid, "$rdmux", i, "", j, "", k, "$b"), mem.width));
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next_rd_signals.push_back(c->getPort(ID::A));
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next_rd_signals.push_back(c->getPort(ID::B));
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}
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next_rd_signals.swap(rd_signals);
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}
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for (int j = 0; j < mem.size; j++)
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module->connect(RTLIL::SigSig(rd_signals[j], data_reg_out[j]));
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}
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log(" read interface: %d $dff and %d $mux cells.\n", count_dff, count_mux);
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for (int i = 0; i < mem.size; i++)
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{
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if (static_cells_map.count(i) > 0)
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continue;
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RTLIL::SigSpec sig = data_reg_out[i];
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for (int j = 0; j < GetSize(mem.wr_ports); j++)
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{
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auto &port = mem.wr_ports[j];
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RTLIL::SigSpec wr_addr = port.addr;
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if (mem.start_offset)
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wr_addr = module->Sub(NEW_ID, wr_addr, SigSpec(mem.start_offset, GetSize(wr_addr)));
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RTLIL::Wire *w_seladdr = addr_decode(wr_addr, RTLIL::SigSpec(i, GetSize(wr_addr)));
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int wr_offset = 0;
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while (wr_offset < port.en.size())
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{
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int wr_width = 1;
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RTLIL::SigSpec wr_bit = port.en.extract(wr_offset, 1);
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while (wr_offset + wr_width < port.en.size()) {
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RTLIL::SigSpec next_wr_bit = port.en.extract(wr_offset + wr_width, 1);
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if (next_wr_bit != wr_bit)
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break;
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wr_width++;
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}
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RTLIL::Wire *w = w_seladdr;
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if (wr_bit != State::S1)
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{
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RTLIL::Cell *c = module->addCell(genid(mem.memid, "$wren", i, "", j, "", wr_offset), ID($and));
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c->parameters[ID::A_SIGNED] = RTLIL::Const(0);
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c->parameters[ID::B_SIGNED] = RTLIL::Const(0);
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c->parameters[ID::A_WIDTH] = RTLIL::Const(1);
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c->parameters[ID::B_WIDTH] = RTLIL::Const(1);
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c->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
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c->setPort(ID::A, w);
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c->setPort(ID::B, wr_bit);
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w = module->addWire(genid(mem.memid, "$wren", i, "", j, "", wr_offset, "$y"));
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c->setPort(ID::Y, RTLIL::SigSpec(w));
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}
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RTLIL::Cell *c = module->addCell(genid(mem.memid, "$wrmux", i, "", j, "", wr_offset), ID($mux));
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c->parameters[ID::WIDTH] = wr_width;
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c->setPort(ID::A, sig.extract(wr_offset, wr_width));
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c->setPort(ID::B, port.data.extract(wr_offset, wr_width));
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c->setPort(ID::S, RTLIL::SigSpec(w));
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w = module->addWire(genid(mem.memid, "$wrmux", i, "", j, "", wr_offset, "$y"), wr_width);
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c->setPort(ID::Y, w);
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sig.replace(wr_offset, w);
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wr_offset += wr_width;
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count_wrmux++;
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}
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}
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module->connect(RTLIL::SigSig(data_reg_in[i], sig));
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}
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log(" write interface: %d write mux blocks.\n", count_wrmux);
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mem.remove();
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}
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void run()
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{
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for (auto &mem : Mem::get_selected_memories(module))
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handle_memory(mem);
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}
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};
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struct MemoryMapPass : public Pass {
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MemoryMapPass() : Pass("memory_map", "translate multiport memories to basic cells") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" memory_map [options] [selection]\n");
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log("\n");
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log("This pass converts multiport memory cells as generated by the memory_collect\n");
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log("pass to word-wide DFFs and address decoders.\n");
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log("\n");
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log(" -attr !<name>\n");
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log(" do not map memories that have attribute <name> set.\n");
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log("\n");
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log(" -attr <name>[=<value>]\n");
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log(" for memories that have attribute <name> set, only map them if its value\n");
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log(" is a string <value> (if specified), or an integer 1 (otherwise). if this\n");
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log(" option is specified multiple times, map the memory if the attribute is\n");
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log(" to any of the values.\n");
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log("\n");
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log(" -iattr\n");
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log(" for -attr, ignore case of <value>.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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bool attr_icase = false;
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dict<RTLIL::IdString, std::vector<RTLIL::Const>> attributes;
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log_header(design, "Executing MEMORY_MAP pass (converting memories to logic and flip-flops).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-attr" && argidx + 1 < args.size())
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{
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std::string attr_arg = args[++argidx];
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std::string name;
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RTLIL::Const value;
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size_t eq_at = attr_arg.find('=');
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if (eq_at != std::string::npos) {
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name = attr_arg.substr(0, eq_at);
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value = attr_arg.substr(eq_at + 1);
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} else {
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name = attr_arg;
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value = RTLIL::Const(1);
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}
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if (attr_arg.size() > 1 && attr_arg[0] == '!') {
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if (value != RTLIL::Const(1)) {
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--argidx;
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break; // we don't support -attr !<name>=<value>
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}
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attributes[RTLIL::escape_id(name.substr(1))].clear();
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} else {
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attributes[RTLIL::escape_id(name)].push_back(value);
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}
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continue;
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}
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if (args[argidx] == "-iattr")
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{
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attr_icase = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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for (auto mod : design->selected_modules()) {
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MemoryMapWorker worker(design, mod);
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worker.attr_icase = attr_icase;
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worker.attributes = attributes;
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worker.run();
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}
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}
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} MemoryMapPass;
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PRIVATE_NAMESPACE_END
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