mirror of https://github.com/YosysHQ/yosys.git
107 lines
2.7 KiB
Plaintext
107 lines
2.7 KiB
Plaintext
library(test) {
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/* Integrated clock gating cells */
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cell (pos_big) {
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area : 10;
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clock_gating_integrated_cell : latch_posedge;
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pin (GCLK) {
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clock_gate_out_pin : true;
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direction : output;
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}
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pin (CLK) {
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clock_gate_clock_pin : true;
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direction : input;
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}
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pin (CE) {
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clock_gate_enable_pin : true;
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direction : input;
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}
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}
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cell (pos_small_tielo) {
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area : 1;
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clock_gating_integrated_cell : latch_posedge_precontrol;
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pin (GCLK) {
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clock_gate_out_pin : true;
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direction : output;
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}
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pin (CLK) {
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clock_gate_clock_pin : true;
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direction : input;
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}
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pin (CE) {
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clock_gate_enable_pin : true;
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direction : input;
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}
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pin (SE) {
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clock_gate_test_pin : true;
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direction : input;
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}
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}
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cell (pos_small) {
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area : 1;
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clock_gating_integrated_cell : latch_posedge;
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pin (GCLK) {
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clock_gate_out_pin : true;
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direction : output;
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}
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pin (CLK) {
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clock_gate_clock_pin : true;
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direction : input;
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}
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pin (CE) {
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clock_gate_enable_pin : true;
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direction : input;
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}
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}
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cell (neg_big) {
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area : 10;
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clock_gating_integrated_cell : latch_negedge;
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pin (GCLK) {
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clock_gate_out_pin : true;
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direction : output;
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}
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pin (CLK) {
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clock_gate_clock_pin : true;
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direction : input;
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}
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pin (CE) {
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clock_gate_enable_pin : true;
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direction : input;
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}
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}
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cell (neg_small_tielo) {
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area : 1;
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clock_gating_integrated_cell : latch_negedge_precontrol;
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pin (GCLK) {
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clock_gate_out_pin : true;
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direction : output;
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}
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pin (CLK) {
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clock_gate_clock_pin : true;
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direction : input;
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}
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pin (CE) {
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clock_gate_enable_pin : true;
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direction : input;
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}
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pin (SE) {
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clock_gate_test_pin : true;
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direction : input;
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}
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}
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cell (neg_small) {
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area : 1;
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clock_gating_integrated_cell : latch_negedge;
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pin (GCLK) {
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clock_gate_out_pin : true;
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direction : output;
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}
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pin (CLK) {
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clock_gate_clock_pin : true;
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direction : input;
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}
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pin (CE) {
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clock_gate_enable_pin : true;
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direction : input;
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}
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}
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} |