mirror of https://github.com/YosysHQ/yosys.git
287 lines
8.7 KiB
C++
287 lines
8.7 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/modtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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//get the list of cells hooked up to at least one bit of a given net
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pool<Cell*> get_other_cells(const RTLIL::SigSpec& port, ModIndex& index, Cell* src)
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{
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pool<Cell*> rval;
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for(auto b : port)
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{
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pool<ModIndex::PortInfo> ports = index.query_ports(b);
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for(auto x : ports)
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{
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if(x.cell == src)
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continue;
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rval.insert(x.cell);
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}
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}
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return rval;
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}
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//return true if there is a full-width bus connection from cell a port ap to cell b port bp
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//if other_conns_allowed is false, then we require a strict point to point connection (no other links)
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bool is_full_bus(
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const RTLIL::SigSpec& sig,
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ModIndex& index,
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Cell* a,
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RTLIL::IdString ap,
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Cell* b,
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RTLIL::IdString bp,
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bool other_conns_allowed = false)
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{
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for(auto s : sig)
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{
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pool<ModIndex::PortInfo> ports = index.query_ports(s);
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bool found_a = false;
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bool found_b = false;
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for(auto x : ports)
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{
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if( (x.cell == a) && (x.port == ap) )
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found_a = true;
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else if( (x.cell == b) && (x.port == bp) )
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found_b = true;
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else if(!other_conns_allowed)
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return false;
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}
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if( (!found_a) || (!found_b) )
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return false;
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}
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return true;
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}
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//return true if the signal connects to one port only (nothing on the other end)
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bool is_unconnected(const RTLIL::SigSpec& port, ModIndex& index)
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{
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for(auto b : port)
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{
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pool<ModIndex::PortInfo> ports = index.query_ports(b);
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if(ports.size() > 1)
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return false;
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}
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return true;
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}
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void greenpak4_counters_worker(ModIndex& index, Module *module, Cell *cell, unsigned int& total_counters)
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{
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SigMap& sigmap = index.sigmap;
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//Core of the counter must be an ALU
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if (cell->type != "$alu")
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return;
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//GreenPak does not support counters larger than 14 bits so immediately skip anything bigger
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int a_width = cell->getParam("\\A_WIDTH").as_int();
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if(a_width > 14)
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return;
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//Second input must be a single bit
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int b_width = cell->getParam("\\B_WIDTH").as_int();
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if(b_width != 1)
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return;
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//Both inputs must be unsigned, so don't extract anything with a signed input
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bool a_sign = cell->getParam("\\A_SIGNED").as_bool();
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bool b_sign = cell->getParam("\\B_SIGNED").as_bool();
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if(a_sign || b_sign)
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return;
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//To be a counter, one input of the ALU must be a constant 1
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//TODO: can A or B be swapped in synthesized RTL or is B always the 1?
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const RTLIL::SigSpec b_port = sigmap(cell->getPort("\\B"));
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if(!b_port.is_fully_const() || (b_port.as_int() != 1) )
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return;
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//BI and CI must be constant 1 as well
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const RTLIL::SigSpec bi_port = sigmap(cell->getPort("\\BI"));
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if(!bi_port.is_fully_const() || (bi_port.as_int() != 1) )
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return;
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const RTLIL::SigSpec ci_port = sigmap(cell->getPort("\\CI"));
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if(!ci_port.is_fully_const() || (ci_port.as_int() != 1) )
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return;
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//CO and X must be unconnected (exactly one connection to each port)
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if(!is_unconnected(sigmap(cell->getPort("\\CO")), index))
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return;
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if(!is_unconnected(sigmap(cell->getPort("\\X")), index))
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return;
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//Y must have exactly one connection, and it has to be a $mux cell.
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//We must have a direct bus connection from our Y to their A.
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const RTLIL::SigSpec aluy = sigmap(cell->getPort("\\Y"));
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pool<Cell*> y_loads = get_other_cells(aluy, index, cell);
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if(y_loads.size() != 1)
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return;
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Cell* count_mux = *y_loads.begin();
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if(count_mux->type != "$mux")
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return;
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if(!is_full_bus(aluy, index, cell, "\\Y", count_mux, "\\A"))
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return;
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//B connection of the mux is our underflow value
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const RTLIL::SigSpec underflow = sigmap(count_mux->getPort("\\B"));
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if(!underflow.is_fully_const())
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return;
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int count_value = underflow.as_int();
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//S connection of the mux must come from an inverter (need not be the only load)
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const RTLIL::SigSpec muxsel = sigmap(count_mux->getPort("\\S"));
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pool<Cell*> muxsel_conns = get_other_cells(muxsel, index, count_mux);
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Cell* underflow_inv = NULL;
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for(auto c : muxsel_conns)
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{
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if(c->type != "$logic_not")
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continue;
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if(!is_full_bus(muxsel, index, c, "\\Y", count_mux, "\\S", true))
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continue;
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underflow_inv = c;
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break;
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}
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if(underflow_inv == NULL)
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return;
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//Y connection of the mux must have exactly one load, the counter's internal register
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const RTLIL::SigSpec muxy = sigmap(count_mux->getPort("\\Y"));
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pool<Cell*> muxy_loads = get_other_cells(muxy, index, count_mux);
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if(muxy_loads.size() != 1)
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return;
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Cell* count_reg = *muxy_loads.begin();
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if(count_reg->type != "$dff") //TODO: support dffr/dffs?
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return;
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if(!is_full_bus(muxy, index, count_mux, "\\Y", count_reg, "\\D"))
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return;
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//Register output must have exactly two loads, the inverter and ALU
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const RTLIL::SigSpec cnout = sigmap(count_reg->getPort("\\Q"));
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pool<Cell*> cnout_loads = get_other_cells(cnout, index, count_reg);
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if(cnout_loads.size() != 2)
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return;
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if(!is_full_bus(cnout, index, count_reg, "\\Q", underflow_inv, "\\A", true))
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return;
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if(!is_full_bus(cnout, index, count_reg, "\\Q", cell, "\\A", true))
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return;
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//Look up the clock from the register
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const RTLIL::SigSpec clk = sigmap(count_reg->getPort("\\CLK"));
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//Register output net must have an INIT attribute equal to the count value
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auto rwire = cnout.as_wire();
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if(rwire->attributes.find("\\init") == rwire->attributes.end())
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return;
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int rinit = rwire->attributes["\\init"].as_int();
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if(rinit != count_value)
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return;
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//Figure out the final cell type based on the counter size
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string celltype = "\\GP_COUNT8";
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if(a_width > 8)
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celltype = "\\GP_COUNT14";
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//Log it
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total_counters ++;
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string count_reg_src = rwire->attributes["\\src"].decode_string().c_str();
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log(" Found %d-bit non-resettable down counter (from %d) for register %s declared at %s\n",
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a_width,
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count_value,
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log_id(rwire->name),
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count_reg_src.c_str());
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//Wipe all of the old connections to the ALU
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cell->unsetPort("\\A");
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cell->unsetPort("\\B");
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cell->unsetPort("\\BI");
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cell->unsetPort("\\CI");
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cell->unsetPort("\\CO");
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cell->unsetPort("\\X");
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cell->unsetPort("\\Y");
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cell->unsetParam("\\A_SIGNED");
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cell->unsetParam("\\A_WIDTH");
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cell->unsetParam("\\B_SIGNED");
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cell->unsetParam("\\B_WIDTH");
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cell->unsetParam("\\Y_WIDTH");
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//Change the cell type
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cell->type = celltype;
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//Hook it up to everything
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cell->setParam("\\RESET_MODE", RTLIL::Const("RISING"));
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cell->setParam("\\CLKIN_DIVIDE", RTLIL::Const(1));
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cell->setParam("\\COUNT_TO", RTLIL::Const(count_value));
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cell->setPort("\\CLK", clk);
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cell->setPort("\\RST", RTLIL::SigSpec(false));
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cell->setPort("\\OUT", muxsel);
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//Delete the cells we've replaced (let opt_clean handle deleting the now-redundant wires)
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module->remove(count_mux);
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module->remove(count_reg);
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module->remove(underflow_inv);
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}
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struct Greenpak4CountersPass : public Pass {
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Greenpak4CountersPass() : Pass("greenpak4_counters", "Extract GreenPak4 counter cells") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" greenpak4_counters [options] [selection]\n");
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log("\n");
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log("This pass converts non-resettable down counters to GreenPak4 counter cells\n");
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log("(All other GreenPak4 counter modes must be instantiated manually for now.)\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header("Executing GREENPAK4_COUNTERS pass (mapping counters to hard IP blocks).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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// if (args[argidx] == "-v") {
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// continue;
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// }
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break;
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}
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extra_args(args, argidx, design);
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unsigned int total_counters = 0;
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for (auto module : design->selected_modules())
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{
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ModIndex index(module);
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for (auto cell : module->selected_cells())
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greenpak4_counters_worker(index, module, cell, total_counters);
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}
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if(total_counters)
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log("Extracted %u counters\n", total_counters);
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}
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} Greenpak4CountersPass;
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PRIVATE_NAMESPACE_END
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