mirror of https://github.com/YosysHQ/yosys.git
92 lines
2.1 KiB
Plaintext
92 lines
2.1 KiB
Plaintext
# test: acceptable for output IOFF promotion
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read_verilog <<EOF
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module top (input clk, input a, output reg o);
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always @(posedge clk) begin
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o <= ~a;
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end
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endmodule
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EOF
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synth_quicklogic -family qlf_k6n10f -top top
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select -assert-count 1 t:dff
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design -reset
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# test: acceptable for input IOFF promotion
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read_verilog <<EOF
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module top (input clk, input a, output o);
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reg r;
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always @(posedge clk) begin
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r <= a;
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end
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assign o = ~r;
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endmodule
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EOF
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synth_quicklogic -family qlf_k6n10f -top top
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select -assert-count 1 t:dff
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design -reset
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# test: acceptable for either IOFF promotion
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read_verilog <<EOF
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module top (input clk, input a, output reg o);
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always @(posedge clk) begin
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o <= a;
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end
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endmodule
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EOF
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synth_quicklogic -family qlf_k6n10f -top top
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select -assert-count 1 t:dff
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design -reset
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# test: not acceptable for output IOFF promotion: output signal is used
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read_verilog <<EOF
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module top (input clk, input a, output reg o);
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always @(posedge clk) begin
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o <= ~a | o;
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end
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endmodule
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EOF
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synth_quicklogic -family qlf_k6n10f -top top
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select -assert-count 0 t:dff
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design -reset
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# test: not acceptable for input IOFF promotion: input signal is used
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read_verilog <<EOF
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module top (input clk, input a, output o, p);
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reg r;
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always @(posedge clk) begin
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r <= a;
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end
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assign o = ~r;
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assign p = ~a;
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endmodule
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EOF
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synth_quicklogic -family qlf_k6n10f -top top
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select -assert-count 0 t:dff
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design -reset
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# test: not acceptable for IOFF promotion: FF has reset
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read_verilog <<EOF
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module top (input clk, input rst, input a, output reg o);
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always @(posedge clk) begin
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if (rst)
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o <= 1'b0;
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else
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o <= a;
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end
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endmodule
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EOF
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synth_quicklogic -family qlf_k6n10f -top top
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select -assert-count 0 t:dff
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design -reset
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# test: not acceptable for IOFF promotion: FF has enable
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read_verilog <<EOF
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module top (input clk, input en, input a, output reg o);
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always @(posedge clk) begin
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if (en)
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o <= a;
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end
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endmodule
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EOF
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synth_quicklogic -family qlf_k6n10f -top top
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select -assert-count 0 t:dff
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