mirror of https://github.com/YosysHQ/yosys.git
186 lines
7.2 KiB
C++
186 lines
7.2 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/ffinit.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct ZinitPass : public Pass {
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ZinitPass() : Pass("zinit", "add inverters so all FF are zero-initialized") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" zinit [options] [selection]\n");
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log("\n");
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log("Add inverters as needed to make all FFs zero-initialized.\n");
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log("\n");
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log(" -all\n");
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log(" also add zero initialization to uninitialized FFs\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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bool all_mode = false;
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log_header(design, "Executing ZINIT pass (make all FFs zero-initialized).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-all") {
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all_mode = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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{
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SigMap sigmap(module);
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FfInitVals initvals(&sigmap, module);
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pool<IdString> dff_types = {
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// FIXME: It would appear that supporting
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// $dffsr/$_DFFSR_* would require a new
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// cell type where S has priority over R
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ID($ff), ID($dff), ID($dffe), /*ID($dffsr),*/ ID($adff), ID($adffe),
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ID($sdff), ID($sdffe), ID($sdffce),
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ID($_FF_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_),
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/*ID($_DFFSR_NNN_), ID($_DFFSR_NNP_), ID($_DFFSR_NPN_), ID($_DFFSR_NPP_),
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ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_),*/
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ID($_DFF_N_), ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
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ID($_DFF_P_), ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_),
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// Async set/reset
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ID($_DFFE_NN0P_), ID($_DFFE_NN1P_), ID($_DFFE_NP0P_), ID($_DFFE_NP1P_),
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ID($_DFFE_PN0P_), ID($_DFFE_PN1P_), ID($_DFFE_PP0P_), ID($_DFFE_PP1P_),
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ID($_DFFE_NN0N_), ID($_DFFE_NN1N_), ID($_DFFE_NP0N_), ID($_DFFE_NP1N_),
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ID($_DFFE_PN0N_), ID($_DFFE_PN1N_), ID($_DFFE_PP0N_), ID($_DFFE_PP1N_),
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// Sync set/reset
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ID($_SDFF_NN0_), ID($_SDFF_NN1_), ID($_SDFF_NP0_), ID($_SDFF_NP1_),
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ID($_SDFF_PN0_), ID($_SDFF_PN1_), ID($_SDFF_PP0_), ID($_SDFF_PP1_),
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ID($_SDFFE_NN0P_), ID($_SDFFE_NN1P_), ID($_SDFFE_NP0P_), ID($_SDFFE_NP1P_),
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ID($_SDFFE_PN0P_), ID($_SDFFE_PN1P_), ID($_SDFFE_PP0P_), ID($_SDFFE_PP1P_),
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ID($_SDFFE_NN0N_), ID($_SDFFE_NN1N_), ID($_SDFFE_NP0N_), ID($_SDFFE_NP1N_),
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ID($_SDFFE_PN0N_), ID($_SDFFE_PN1N_), ID($_SDFFE_PP0N_), ID($_SDFFE_PP1N_),
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ID($_SDFFCE_NN0P_), ID($_SDFFCE_NN1P_), ID($_SDFFCE_NP0P_), ID($_SDFFCE_NP1P_),
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ID($_SDFFCE_PN0P_), ID($_SDFFCE_PN1P_), ID($_SDFFCE_PP0P_), ID($_SDFFCE_PP1P_),
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ID($_SDFFCE_NN0N_), ID($_SDFFCE_NN1N_), ID($_SDFFCE_NP0N_), ID($_SDFFCE_NP1N_),
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ID($_SDFFCE_PN0N_), ID($_SDFFCE_PN1N_), ID($_SDFFCE_PP0N_), ID($_SDFFCE_PP1N_)
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};
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for (auto cell : module->selected_cells())
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{
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if (!dff_types.count(cell->type))
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continue;
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SigSpec sig_d = sigmap(cell->getPort(ID::D));
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SigSpec sig_q = sigmap(cell->getPort(ID::Q));
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if (GetSize(sig_d) < 1 || GetSize(sig_q) < 1)
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continue;
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Const initval = initvals(sig_q);
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Const newval = initval;
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initvals.remove_init(sig_q);
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Wire *initwire = module->addWire(NEW_ID, GetSize(sig_q));
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for (int i = 0; i < GetSize(initwire); i++)
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if (initval[i] == State::S1)
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{
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sig_d[i] = module->NotGate(NEW_ID, sig_d[i]);
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module->addNotGate(NEW_ID, SigSpec(initwire, i), sig_q[i]);
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newval[i] = State::S0;
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}
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else
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{
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module->connect(sig_q[i], SigSpec(initwire, i));
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if (all_mode)
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newval[i] = State::S0;
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}
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initvals.set_init(initwire, newval);
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log("FF init value for cell %s (%s): %s = %s\n", log_id(cell), log_id(cell->type),
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log_signal(sig_q), log_signal(initval));
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cell->setPort(ID::D, sig_d);
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cell->setPort(ID::Q, initwire);
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if (cell->type.in(ID($adff), ID($adffe))) {
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auto val = cell->getParam(ID::ARST_VALUE);
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for (int i = 0; i < GetSize(initwire); i++)
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if (initval[i] == State::S1)
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val[i] = (val[i] == State::S1 ? State::S0 : State::S1);
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cell->setParam(ID::ARST_VALUE, std::move(val));
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}
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else if (cell->type.in(ID($sdff), ID($sdffe), ID($sdffce))) {
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auto val = cell->getParam(ID::SRST_VALUE);
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for (int i = 0; i < GetSize(initwire); i++)
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if (initval[i] == State::S1)
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val[i] = (val[i] == State::S1 ? State::S0 : State::S1);
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cell->setParam(ID::SRST_VALUE, std::move(val));
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}
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else if (initval == State::S1) {
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std::string t = cell->type.str();
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if (cell->type.in(ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
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ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_)))
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{
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t[8] = (t[8] == '0' ? '1' : '0');
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}
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else if (cell->type.in(ID($_SDFF_NN0_), ID($_SDFF_NN1_), ID($_SDFF_NP0_), ID($_SDFF_NP1_),
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ID($_SDFF_PN0_), ID($_SDFF_PN1_), ID($_SDFF_PP0_), ID($_SDFF_PP1_)))
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{
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t[9] = (t[9] == '0' ? '1' : '0');
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}
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else if (cell->type.in(ID($_DFFE_NN0P_), ID($_DFFE_NN1P_), ID($_DFFE_NP0P_), ID($_DFFE_NP1P_),
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ID($_DFFE_PN0P_), ID($_DFFE_PN1P_), ID($_DFFE_PP0P_), ID($_DFFE_PP1P_),
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ID($_DFFE_NN0N_), ID($_DFFE_NN1N_), ID($_DFFE_NP0N_), ID($_DFFE_NP1N_),
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ID($_DFFE_PN0N_), ID($_DFFE_PN1N_), ID($_DFFE_PP0N_), ID($_DFFE_PP1N_)))
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{
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t[9] = (t[9] == '0' ? '1' : '0');
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}
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else if (cell->type.in(ID($_SDFFE_NN0P_), ID($_SDFFE_NN1P_), ID($_SDFFE_NP0P_), ID($_SDFFE_NP1P_),
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ID($_SDFFE_PN0P_), ID($_SDFFE_PN1P_), ID($_SDFFE_PP0P_), ID($_SDFFE_PP1P_),
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ID($_SDFFE_NN0N_), ID($_SDFFE_NN1N_), ID($_SDFFE_NP0N_), ID($_SDFFE_NP1N_),
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ID($_SDFFE_PN0N_), ID($_SDFFE_PN1N_), ID($_SDFFE_PP0N_), ID($_SDFFE_PP1N_)))
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{
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t[10] = (t[10] == '0' ? '1' : '0');
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}
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else if (cell->type.in(ID($_SDFFCE_NN0P_), ID($_SDFFCE_NN1P_), ID($_SDFFCE_NP0P_), ID($_SDFFCE_NP1P_),
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ID($_SDFFCE_PN0P_), ID($_SDFFCE_PN1P_), ID($_SDFFCE_PP0P_), ID($_SDFFCE_PP1P_),
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ID($_SDFFCE_NN0N_), ID($_SDFFCE_NN1N_), ID($_SDFFCE_NP0N_), ID($_SDFFCE_NP1N_),
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ID($_SDFFCE_PN0N_), ID($_SDFFCE_PN1N_), ID($_SDFFCE_PP0N_), ID($_SDFFCE_PP1N_)))
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{
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t[11] = (t[11] == '0' ? '1' : '0');
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}
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cell->type = t;
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}
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}
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}
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}
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} ZinitPass;
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PRIVATE_NAMESPACE_END
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