mirror of https://github.com/YosysHQ/yosys.git
16 lines
483 B
Verilog
16 lines
483 B
Verilog
module \$__BEYOND_IBUF (input PAD, output O);
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NX_IOB_I _TECHMAP_REPLACE_ (.IO(PAD), .O(O), .C(1'b0));
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endmodule
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module \$__BEYOND_OBUF (output PAD, input I);
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NX_IOB_O _TECHMAP_REPLACE_ (.IO(PAD), .I(I), .C(1'b1));
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endmodule
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module \$__BEYOND_TOBUF (output PAD, input I, input C);
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NX_IOB _TECHMAP_REPLACE_ (.IO(PAD), .I(I), .C(C));
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endmodule
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module \$__BEYOND_IOBUF (output PAD, input I, output O, output C);
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NX_IOB _TECHMAP_REPLACE_ (.IO(PAD), .I(I), .O(O), .C(C));
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endmodule
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