mirror of https://github.com/YosysHQ/yosys.git
1957 lines
86 KiB
C++
1957 lines
86 KiB
C++
/* -*- c++ -*-
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef RTLIL_H
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#define RTLIL_H
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#include "kernel/yosys_common.h"
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#include "kernel/yosys.h"
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YOSYS_NAMESPACE_BEGIN
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namespace RTLIL
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{
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enum State : unsigned char {
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S0 = 0,
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S1 = 1,
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Sx = 2, // undefined value or conflict
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Sz = 3, // high-impedance / not-connected
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Sa = 4, // don't care (used only in cases)
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Sm = 5 // marker (used internally by some passes)
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};
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enum SyncType : unsigned char {
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ST0 = 0, // level sensitive: 0
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ST1 = 1, // level sensitive: 1
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STp = 2, // edge sensitive: posedge
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STn = 3, // edge sensitive: negedge
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STe = 4, // edge sensitive: both edges
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STa = 5, // always active
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STg = 6, // global clock
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STi = 7 // init
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};
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// Semantic metadata - how can this constant be interpreted?
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// Values may be generally non-exclusive
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enum ConstFlags : unsigned char {
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CONST_FLAG_NONE = 0,
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CONST_FLAG_STRING = 1,
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CONST_FLAG_SIGNED = 2, // only used for parameters
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CONST_FLAG_REAL = 4 // only used for parameters
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};
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struct Const;
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struct AttrObject;
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struct Selection;
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struct Monitor;
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struct Design;
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struct Module;
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struct Wire;
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struct Memory;
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struct Cell;
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struct SigChunk;
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struct SigBit;
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struct SigSpecIterator;
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struct SigSpecConstIterator;
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struct SigSpec;
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struct CaseRule;
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struct SwitchRule;
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struct MemWriteAction;
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struct SyncRule;
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struct Process;
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struct Binding;
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typedef std::pair<SigSpec, SigSpec> SigSig;
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struct IdString
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{
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#undef YOSYS_XTRACE_GET_PUT
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#undef YOSYS_SORT_ID_FREE_LIST
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#undef YOSYS_USE_STICKY_IDS
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#undef YOSYS_NO_IDS_REFCNT
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// the global id string cache
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static bool destruct_guard_ok; // POD, will be initialized to zero
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static struct destruct_guard_t {
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destruct_guard_t() { destruct_guard_ok = true; }
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~destruct_guard_t() { destruct_guard_ok = false; }
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} destruct_guard;
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static std::vector<char*> global_id_storage_;
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static dict<char*, int, hash_cstr_ops> global_id_index_;
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#ifndef YOSYS_NO_IDS_REFCNT
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static std::vector<int> global_refcount_storage_;
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static std::vector<int> global_free_idx_list_;
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#endif
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#ifdef YOSYS_USE_STICKY_IDS
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static int last_created_idx_ptr_;
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static int last_created_idx_[8];
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#endif
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static inline void xtrace_db_dump()
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{
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#ifdef YOSYS_XTRACE_GET_PUT
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for (int idx = 0; idx < GetSize(global_id_storage_); idx++)
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{
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if (global_id_storage_.at(idx) == nullptr)
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log("#X# DB-DUMP index %d: FREE\n", idx);
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else
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log("#X# DB-DUMP index %d: '%s' (ref %d)\n", idx, global_id_storage_.at(idx), global_refcount_storage_.at(idx));
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}
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#endif
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}
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static inline void checkpoint()
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{
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#ifdef YOSYS_USE_STICKY_IDS
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last_created_idx_ptr_ = 0;
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for (int i = 0; i < 8; i++) {
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if (last_created_idx_[i])
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put_reference(last_created_idx_[i]);
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last_created_idx_[i] = 0;
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}
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#endif
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#ifdef YOSYS_SORT_ID_FREE_LIST
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std::sort(global_free_idx_list_.begin(), global_free_idx_list_.end(), std::greater<int>());
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#endif
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}
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static inline int get_reference(int idx)
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{
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if (idx) {
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#ifndef YOSYS_NO_IDS_REFCNT
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global_refcount_storage_[idx]++;
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#endif
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#ifdef YOSYS_XTRACE_GET_PUT
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if (yosys_xtrace)
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log("#X# GET-BY-INDEX '%s' (index %d, refcount %d)\n", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));
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#endif
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}
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return idx;
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}
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static int get_reference(const char *p)
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{
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log_assert(destruct_guard_ok);
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if (!p[0])
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return 0;
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auto it = global_id_index_.find((char*)p);
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if (it != global_id_index_.end()) {
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#ifndef YOSYS_NO_IDS_REFCNT
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global_refcount_storage_.at(it->second)++;
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#endif
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#ifdef YOSYS_XTRACE_GET_PUT
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if (yosys_xtrace)
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log("#X# GET-BY-NAME '%s' (index %d, refcount %d)\n", global_id_storage_.at(it->second), it->second, global_refcount_storage_.at(it->second));
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#endif
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return it->second;
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}
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log_assert(p[0] == '$' || p[0] == '\\');
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log_assert(p[1] != 0);
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for (const char *c = p; *c; c++)
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if ((unsigned)*c <= (unsigned)' ')
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log_error("Found control character or space (0x%02x) in string '%s' which is not allowed in RTLIL identifiers\n", *c, p);
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#ifndef YOSYS_NO_IDS_REFCNT
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if (global_free_idx_list_.empty()) {
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if (global_id_storage_.empty()) {
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global_refcount_storage_.push_back(0);
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global_id_storage_.push_back((char*)"");
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global_id_index_[global_id_storage_.back()] = 0;
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}
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log_assert(global_id_storage_.size() < 0x40000000);
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global_free_idx_list_.push_back(global_id_storage_.size());
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global_id_storage_.push_back(nullptr);
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global_refcount_storage_.push_back(0);
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}
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int idx = global_free_idx_list_.back();
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global_free_idx_list_.pop_back();
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global_id_storage_.at(idx) = strdup(p);
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global_id_index_[global_id_storage_.at(idx)] = idx;
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global_refcount_storage_.at(idx)++;
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#else
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if (global_id_storage_.empty()) {
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global_id_storage_.push_back((char*)"");
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global_id_index_[global_id_storage_.back()] = 0;
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}
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int idx = global_id_storage_.size();
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global_id_storage_.push_back(strdup(p));
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global_id_index_[global_id_storage_.back()] = idx;
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#endif
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if (yosys_xtrace) {
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log("#X# New IdString '%s' with index %d.\n", p, idx);
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log_backtrace("-X- ", yosys_xtrace-1);
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}
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#ifdef YOSYS_XTRACE_GET_PUT
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if (yosys_xtrace)
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log("#X# GET-BY-NAME '%s' (index %d, refcount %d)\n", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));
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#endif
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#ifdef YOSYS_USE_STICKY_IDS
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// Avoid Create->Delete->Create pattern
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if (last_created_idx_[last_created_idx_ptr_])
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put_reference(last_created_idx_[last_created_idx_ptr_]);
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last_created_idx_[last_created_idx_ptr_] = idx;
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get_reference(last_created_idx_[last_created_idx_ptr_]);
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last_created_idx_ptr_ = (last_created_idx_ptr_ + 1) & 7;
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#endif
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return idx;
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}
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#ifndef YOSYS_NO_IDS_REFCNT
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static inline void put_reference(int idx)
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{
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// put_reference() may be called from destructors after the destructor of
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// global_refcount_storage_ has been run. in this case we simply do nothing.
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if (!destruct_guard_ok || !idx)
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return;
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#ifdef YOSYS_XTRACE_GET_PUT
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if (yosys_xtrace) {
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log("#X# PUT '%s' (index %d, refcount %d)\n", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));
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}
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#endif
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int &refcount = global_refcount_storage_[idx];
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if (--refcount > 0)
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return;
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log_assert(refcount == 0);
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free_reference(idx);
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}
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static inline void free_reference(int idx)
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{
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if (yosys_xtrace) {
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log("#X# Removed IdString '%s' with index %d.\n", global_id_storage_.at(idx), idx);
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log_backtrace("-X- ", yosys_xtrace-1);
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}
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global_id_index_.erase(global_id_storage_.at(idx));
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free(global_id_storage_.at(idx));
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global_id_storage_.at(idx) = nullptr;
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global_free_idx_list_.push_back(idx);
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}
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#else
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static inline void put_reference(int) { }
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#endif
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// the actual IdString object is just is a single int
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int index_;
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inline IdString() : index_(0) { }
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inline IdString(const char *str) : index_(get_reference(str)) { }
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inline IdString(const IdString &str) : index_(get_reference(str.index_)) { }
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inline IdString(IdString &&str) : index_(str.index_) { str.index_ = 0; }
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inline IdString(const std::string &str) : index_(get_reference(str.c_str())) { }
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inline ~IdString() { put_reference(index_); }
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inline void operator=(const IdString &rhs) {
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put_reference(index_);
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index_ = get_reference(rhs.index_);
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}
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inline void operator=(const char *rhs) {
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IdString id(rhs);
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*this = id;
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}
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inline void operator=(const std::string &rhs) {
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IdString id(rhs);
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*this = id;
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}
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inline const char *c_str() const {
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return global_id_storage_.at(index_);
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}
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inline std::string str() const {
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return std::string(global_id_storage_.at(index_));
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}
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inline bool operator<(const IdString &rhs) const {
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return index_ < rhs.index_;
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}
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inline bool operator==(const IdString &rhs) const { return index_ == rhs.index_; }
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inline bool operator!=(const IdString &rhs) const { return index_ != rhs.index_; }
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// The methods below are just convenience functions for better compatibility with std::string.
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bool operator==(const std::string &rhs) const { return c_str() == rhs; }
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bool operator!=(const std::string &rhs) const { return c_str() != rhs; }
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bool operator==(const char *rhs) const { return strcmp(c_str(), rhs) == 0; }
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bool operator!=(const char *rhs) const { return strcmp(c_str(), rhs) != 0; }
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char operator[](size_t i) const {
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const char *p = c_str();
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#ifndef NDEBUG
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for (; i != 0; i--, p++)
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log_assert(*p != 0);
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return *p;
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#else
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return *(p + i);
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#endif
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}
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std::string substr(size_t pos = 0, size_t len = std::string::npos) const {
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if (len == std::string::npos || len >= strlen(c_str() + pos))
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return std::string(c_str() + pos);
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else
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return std::string(c_str() + pos, len);
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}
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int compare(size_t pos, size_t len, const char* s) const {
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return strncmp(c_str()+pos, s, len);
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}
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bool begins_with(const char* prefix) const {
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size_t len = strlen(prefix);
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if (size() < len) return false;
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return compare(0, len, prefix) == 0;
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}
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bool ends_with(const char* suffix) const {
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size_t len = strlen(suffix);
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if (size() < len) return false;
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return compare(size()-len, len, suffix) == 0;
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}
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bool contains(const char* str) const {
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return strstr(c_str(), str);
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}
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size_t size() const {
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return strlen(c_str());
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}
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bool empty() const {
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return c_str()[0] == 0;
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}
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void clear() {
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*this = IdString();
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}
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unsigned int hash() const {
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return index_;
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}
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// The following is a helper key_compare class. Instead of for example std::set<Cell*>
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// use std::set<Cell*, IdString::compare_ptr_by_name<Cell>> if the order of cells in the
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// set has an influence on the algorithm.
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template<typename T> struct compare_ptr_by_name {
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bool operator()(const T *a, const T *b) const {
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return (a == nullptr || b == nullptr) ? (a < b) : (a->name < b->name);
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}
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};
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// often one needs to check if a given IdString is part of a list (for example a list
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// of cell types). the following functions helps with that.
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template<typename... Args>
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bool in(Args... args) const {
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// Credit: https://articles.emptycrate.com/2016/05/14/folds_in_cpp11_ish.html
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bool result = false;
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(void) std::initializer_list<int>{ (result = result || in(args), 0)... };
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return result;
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}
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bool in(const IdString &rhs) const { return *this == rhs; }
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bool in(const char *rhs) const { return *this == rhs; }
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bool in(const std::string &rhs) const { return *this == rhs; }
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bool in(const pool<IdString> &rhs) const { return rhs.count(*this) != 0; }
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bool isPublic() const { return begins_with("\\"); }
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};
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namespace ID {
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#define X(_id) extern IdString _id;
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#include "kernel/constids.inc"
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#undef X
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};
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extern dict<std::string, std::string> constpad;
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const pool<IdString> &builtin_ff_cell_types();
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static inline std::string escape_id(const std::string &str) {
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if (str.size() > 0 && str[0] != '\\' && str[0] != '$')
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return "\\" + str;
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return str;
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}
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static inline std::string unescape_id(const std::string &str) {
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if (str.size() < 2)
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return str;
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if (str[0] != '\\')
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return str;
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if (str[1] == '$' || str[1] == '\\')
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return str;
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if (str[1] >= '0' && str[1] <= '9')
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return str;
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return str.substr(1);
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}
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static inline std::string unescape_id(const RTLIL::IdString &str) {
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return unescape_id(str.str());
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}
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static inline const char *id2cstr(const RTLIL::IdString &str) {
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return log_id(str);
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}
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template <typename T> struct sort_by_name_id {
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bool operator()(T *a, T *b) const {
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return a->name < b->name;
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}
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};
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template <typename T> struct sort_by_name_str {
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bool operator()(T *a, T *b) const {
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return strcmp(a->name.c_str(), b->name.c_str()) < 0;
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}
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};
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struct sort_by_id_str {
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bool operator()(const RTLIL::IdString &a, const RTLIL::IdString &b) const {
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return strcmp(a.c_str(), b.c_str()) < 0;
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}
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};
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static inline std::string encode_filename(const std::string &filename)
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{
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std::stringstream val;
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if (!std::any_of(filename.begin(), filename.end(), [](char c) {
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return static_cast<unsigned char>(c) < 33 || static_cast<unsigned char>(c) > 126;
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})) return filename;
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for (unsigned char const c : filename) {
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if (c < 33 || c > 126)
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val << stringf("$%02x", c);
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else
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val << c;
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}
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return val.str();
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}
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// see calc.cc for the implementation of this functions
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RTLIL::Const const_not (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_and (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_or (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_xor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_xnor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_reduce_and (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_reduce_or (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_reduce_xor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_reduce_xnor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_reduce_bool (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_logic_not (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_logic_and (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
RTLIL::Const const_logic_or (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
|
|
RTLIL::Const const_shl (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
RTLIL::Const const_shr (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
RTLIL::Const const_sshl (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
RTLIL::Const const_sshr (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
RTLIL::Const const_shift (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
RTLIL::Const const_shiftx (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
|
|
RTLIL::Const const_lt (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
RTLIL::Const const_le (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
RTLIL::Const const_eq (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
RTLIL::Const const_ne (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
RTLIL::Const const_eqx (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
RTLIL::Const const_nex (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
RTLIL::Const const_ge (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
RTLIL::Const const_gt (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
|
|
RTLIL::Const const_add (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
RTLIL::Const const_sub (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
RTLIL::Const const_mul (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
RTLIL::Const const_div (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
RTLIL::Const const_divfloor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
RTLIL::Const const_modfloor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
RTLIL::Const const_mod (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
RTLIL::Const const_pow (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
|
|
RTLIL::Const const_pos (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
RTLIL::Const const_buf (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
RTLIL::Const const_neg (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
|
|
|
|
RTLIL::Const const_mux (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);
|
|
RTLIL::Const const_pmux (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);
|
|
RTLIL::Const const_bmux (const RTLIL::Const &arg1, const RTLIL::Const &arg2);
|
|
RTLIL::Const const_demux (const RTLIL::Const &arg1, const RTLIL::Const &arg2);
|
|
|
|
RTLIL::Const const_bweqx (const RTLIL::Const &arg1, const RTLIL::Const &arg2);
|
|
RTLIL::Const const_bwmux (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3);
|
|
|
|
|
|
// This iterator-range-pair is used for Design::modules(), Module::wires() and Module::cells().
|
|
// It maintains a reference counter that is used to make sure that the container is not modified while being iterated over.
|
|
|
|
template<typename T>
|
|
struct ObjIterator {
|
|
using iterator_category = std::forward_iterator_tag;
|
|
using value_type = T;
|
|
using difference_type = ptrdiff_t;
|
|
using pointer = T*;
|
|
using reference = T&;
|
|
typename dict<RTLIL::IdString, T>::iterator it;
|
|
dict<RTLIL::IdString, T> *list_p;
|
|
int *refcount_p;
|
|
|
|
ObjIterator() : list_p(nullptr), refcount_p(nullptr) {
|
|
}
|
|
|
|
ObjIterator(decltype(list_p) list_p, int *refcount_p) : list_p(list_p), refcount_p(refcount_p) {
|
|
if (list_p->empty()) {
|
|
this->list_p = nullptr;
|
|
this->refcount_p = nullptr;
|
|
} else {
|
|
it = list_p->begin();
|
|
(*refcount_p)++;
|
|
}
|
|
}
|
|
|
|
ObjIterator(const RTLIL::ObjIterator<T> &other) {
|
|
it = other.it;
|
|
list_p = other.list_p;
|
|
refcount_p = other.refcount_p;
|
|
if (refcount_p)
|
|
(*refcount_p)++;
|
|
}
|
|
|
|
ObjIterator &operator=(const RTLIL::ObjIterator<T> &other) {
|
|
if (refcount_p)
|
|
(*refcount_p)--;
|
|
it = other.it;
|
|
list_p = other.list_p;
|
|
refcount_p = other.refcount_p;
|
|
if (refcount_p)
|
|
(*refcount_p)++;
|
|
return *this;
|
|
}
|
|
|
|
~ObjIterator() {
|
|
if (refcount_p)
|
|
(*refcount_p)--;
|
|
}
|
|
|
|
inline T operator*() const {
|
|
log_assert(list_p != nullptr);
|
|
return it->second;
|
|
}
|
|
|
|
inline bool operator!=(const RTLIL::ObjIterator<T> &other) const {
|
|
if (list_p == nullptr || other.list_p == nullptr)
|
|
return list_p != other.list_p;
|
|
return it != other.it;
|
|
}
|
|
|
|
|
|
inline bool operator==(const RTLIL::ObjIterator<T> &other) const {
|
|
return !(*this != other);
|
|
}
|
|
|
|
inline ObjIterator<T>& operator++() {
|
|
log_assert(list_p != nullptr);
|
|
if (++it == list_p->end()) {
|
|
(*refcount_p)--;
|
|
list_p = nullptr;
|
|
refcount_p = nullptr;
|
|
}
|
|
return *this;
|
|
}
|
|
|
|
inline ObjIterator<T>& operator+=(int amt) {
|
|
log_assert(list_p != nullptr);
|
|
it += amt;
|
|
if (it == list_p->end()) {
|
|
(*refcount_p)--;
|
|
list_p = nullptr;
|
|
refcount_p = nullptr;
|
|
}
|
|
return *this;
|
|
}
|
|
|
|
inline ObjIterator<T> operator+(int amt) {
|
|
log_assert(list_p != nullptr);
|
|
ObjIterator<T> new_obj(*this);
|
|
new_obj.it += amt;
|
|
if (new_obj.it == list_p->end()) {
|
|
(*(new_obj.refcount_p))--;
|
|
new_obj.list_p = nullptr;
|
|
new_obj.refcount_p = nullptr;
|
|
}
|
|
return new_obj;
|
|
}
|
|
|
|
inline const ObjIterator<T> operator++(int) {
|
|
ObjIterator<T> result(*this);
|
|
++(*this);
|
|
return result;
|
|
}
|
|
};
|
|
|
|
template<typename T>
|
|
struct ObjRange
|
|
{
|
|
dict<RTLIL::IdString, T> *list_p;
|
|
int *refcount_p;
|
|
|
|
ObjRange(decltype(list_p) list_p, int *refcount_p) : list_p(list_p), refcount_p(refcount_p) { }
|
|
RTLIL::ObjIterator<T> begin() { return RTLIL::ObjIterator<T>(list_p, refcount_p); }
|
|
RTLIL::ObjIterator<T> end() { return RTLIL::ObjIterator<T>(); }
|
|
|
|
size_t size() const {
|
|
return list_p->size();
|
|
}
|
|
|
|
operator pool<T>() const {
|
|
pool<T> result;
|
|
for (auto &it : *list_p)
|
|
result.insert(it.second);
|
|
return result;
|
|
}
|
|
|
|
operator std::vector<T>() const {
|
|
std::vector<T> result;
|
|
result.reserve(list_p->size());
|
|
for (auto &it : *list_p)
|
|
result.push_back(it.second);
|
|
return result;
|
|
}
|
|
|
|
pool<T> to_pool() const { return *this; }
|
|
std::vector<T> to_vector() const { return *this; }
|
|
};
|
|
};
|
|
|
|
struct RTLIL::Const
|
|
{
|
|
short int flags;
|
|
private:
|
|
friend class KernelRtlilTest;
|
|
FRIEND_TEST(KernelRtlilTest, ConstStr);
|
|
using bitvectype = std::vector<RTLIL::State>;
|
|
enum class backing_tag: bool { bits, string };
|
|
// Do not access the union or tag even in Const methods unless necessary
|
|
mutable backing_tag tag;
|
|
union {
|
|
mutable bitvectype bits_;
|
|
mutable std::string str_;
|
|
};
|
|
|
|
// Use these private utilities instead
|
|
bool is_bits() const { return tag == backing_tag::bits; }
|
|
bool is_str() const { return tag == backing_tag::string; }
|
|
|
|
bitvectype* get_if_bits() const { return is_bits() ? &bits_ : NULL; }
|
|
std::string* get_if_str() const { return is_str() ? &str_ : NULL; }
|
|
|
|
bitvectype& get_bits() const;
|
|
std::string& get_str() const;
|
|
public:
|
|
Const() : flags(RTLIL::CONST_FLAG_NONE), tag(backing_tag::bits), bits_(std::vector<RTLIL::State>()) {}
|
|
Const(const std::string &str);
|
|
Const(long long val, int width = 32);
|
|
Const(RTLIL::State bit, int width = 1);
|
|
Const(const std::vector<RTLIL::State> &bits) : flags(RTLIL::CONST_FLAG_NONE), tag(backing_tag::bits), bits_(bits) {}
|
|
Const(const std::vector<bool> &bits);
|
|
Const(const RTLIL::Const &other);
|
|
Const(RTLIL::Const &&other);
|
|
RTLIL::Const &operator =(const RTLIL::Const &other);
|
|
~Const();
|
|
|
|
bool operator <(const RTLIL::Const &other) const;
|
|
bool operator ==(const RTLIL::Const &other) const;
|
|
bool operator !=(const RTLIL::Const &other) const;
|
|
|
|
std::vector<RTLIL::State>& bits();
|
|
bool as_bool() const;
|
|
int as_int(bool is_signed = false) const;
|
|
std::string as_string(const char* any = "-") const;
|
|
static Const from_string(const std::string &str);
|
|
std::vector<RTLIL::State> to_bits() const;
|
|
|
|
std::string decode_string() const;
|
|
int size() const;
|
|
bool empty() const;
|
|
void bitvectorize() const;
|
|
|
|
class const_iterator {
|
|
private:
|
|
const Const& parent;
|
|
size_t idx;
|
|
|
|
public:
|
|
using iterator_category = std::input_iterator_tag;
|
|
using value_type = State;
|
|
using difference_type = std::ptrdiff_t;
|
|
using pointer = const State*;
|
|
using reference = const State&;
|
|
|
|
const_iterator(const Const& c, size_t i) : parent(c), idx(i) {}
|
|
|
|
State operator*() const;
|
|
|
|
const_iterator& operator++() { ++idx; return *this; }
|
|
const_iterator& operator--() { --idx; return *this; }
|
|
const_iterator& operator++(int) { ++idx; return *this; }
|
|
const_iterator& operator--(int) { --idx; return *this; }
|
|
const_iterator& operator+=(int i) { idx += i; return *this; }
|
|
|
|
const_iterator operator+(int add) {
|
|
return const_iterator(parent, idx + add);
|
|
}
|
|
const_iterator operator-(int sub) {
|
|
return const_iterator(parent, idx - sub);
|
|
}
|
|
int operator-(const const_iterator& other) {
|
|
return idx - other.idx;
|
|
}
|
|
|
|
bool operator==(const const_iterator& other) const {
|
|
return idx == other.idx;
|
|
}
|
|
|
|
bool operator!=(const const_iterator& other) const {
|
|
return !(*this == other);
|
|
}
|
|
};
|
|
|
|
const_iterator begin() const {
|
|
return const_iterator(*this, 0);
|
|
}
|
|
const_iterator end() const {
|
|
return const_iterator(*this, size());
|
|
}
|
|
State back() const {
|
|
return *(end() - 1);
|
|
}
|
|
State front() const {
|
|
return *begin();
|
|
}
|
|
State at(size_t i) const {
|
|
return *const_iterator(*this, i);
|
|
}
|
|
State operator[](size_t i) const {
|
|
return *const_iterator(*this, i);
|
|
}
|
|
|
|
bool is_fully_zero() const;
|
|
bool is_fully_ones() const;
|
|
bool is_fully_def() const;
|
|
bool is_fully_undef() const;
|
|
bool is_fully_undef_x_only() const;
|
|
bool is_onehot(int *pos = nullptr) const;
|
|
|
|
RTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const;
|
|
|
|
// find the MSB without redundant leading bits
|
|
size_t get_min_size(bool is_signed) const;
|
|
|
|
// compress representation to the minimum required bits
|
|
void compress(bool is_signed = false);
|
|
|
|
std::optional<int> as_int_compress(bool is_signed) const;
|
|
|
|
void extu(int width) {
|
|
bits().resize(width, RTLIL::State::S0);
|
|
}
|
|
|
|
void exts(int width) {
|
|
bitvectype& bv = bits();
|
|
bv.resize(width, bv.empty() ? RTLIL::State::Sx : bv.back());
|
|
}
|
|
|
|
inline unsigned int hash() const {
|
|
unsigned int h = mkhash_init;
|
|
|
|
for (State b : *this)
|
|
h = mkhash(h, b);
|
|
return h;
|
|
}
|
|
};
|
|
|
|
struct RTLIL::AttrObject
|
|
{
|
|
dict<RTLIL::IdString, RTLIL::Const> attributes;
|
|
|
|
bool has_attribute(const RTLIL::IdString &id) const;
|
|
|
|
void set_bool_attribute(const RTLIL::IdString &id, bool value=true);
|
|
bool get_bool_attribute(const RTLIL::IdString &id) const;
|
|
|
|
bool get_blackbox_attribute(bool ignore_wb=false) const {
|
|
return get_bool_attribute(ID::blackbox) || (!ignore_wb && get_bool_attribute(ID::whitebox));
|
|
}
|
|
|
|
void set_string_attribute(const RTLIL::IdString& id, string value);
|
|
string get_string_attribute(const RTLIL::IdString &id) const;
|
|
|
|
void set_strpool_attribute(const RTLIL::IdString& id, const pool<string> &data);
|
|
void add_strpool_attribute(const RTLIL::IdString& id, const pool<string> &data);
|
|
pool<string> get_strpool_attribute(const RTLIL::IdString &id) const;
|
|
|
|
void set_src_attribute(const std::string &src) {
|
|
set_string_attribute(ID::src, src);
|
|
}
|
|
std::string get_src_attribute() const {
|
|
return get_string_attribute(ID::src);
|
|
}
|
|
|
|
void set_hdlname_attribute(const vector<string> &hierarchy);
|
|
vector<string> get_hdlname_attribute() const;
|
|
|
|
void set_intvec_attribute(const RTLIL::IdString& id, const vector<int> &data);
|
|
vector<int> get_intvec_attribute(const RTLIL::IdString &id) const;
|
|
};
|
|
|
|
struct RTLIL::SigChunk
|
|
{
|
|
RTLIL::Wire *wire;
|
|
std::vector<RTLIL::State> data; // only used if wire == NULL, LSB at index 0
|
|
int width, offset;
|
|
|
|
SigChunk() : wire(nullptr), width(0), offset(0) {}
|
|
SigChunk(const RTLIL::Const &value) : wire(nullptr), data(value.to_bits()), width(GetSize(data)), offset(0) {}
|
|
SigChunk(RTLIL::Const &&value) : wire(nullptr), data(value.to_bits()), width(GetSize(data)), offset(0) {}
|
|
SigChunk(RTLIL::Wire *wire) : wire(wire), width(GetSize(wire)), offset(0) {}
|
|
SigChunk(RTLIL::Wire *wire, int offset, int width = 1) : wire(wire), width(width), offset(offset) {}
|
|
SigChunk(const std::string &str) : SigChunk(RTLIL::Const(str)) {}
|
|
SigChunk(int val, int width = 32) : SigChunk(RTLIL::Const(val, width)) {}
|
|
SigChunk(RTLIL::State bit, int width = 1) : SigChunk(RTLIL::Const(bit, width)) {}
|
|
SigChunk(const RTLIL::SigBit &bit);
|
|
|
|
RTLIL::SigChunk extract(int offset, int length) const;
|
|
RTLIL::SigBit operator[](int offset) const;
|
|
inline int size() const { return width; }
|
|
inline bool is_wire() const { return wire != NULL; }
|
|
|
|
bool operator <(const RTLIL::SigChunk &other) const;
|
|
bool operator ==(const RTLIL::SigChunk &other) const;
|
|
bool operator !=(const RTLIL::SigChunk &other) const;
|
|
};
|
|
|
|
struct RTLIL::SigBit
|
|
{
|
|
RTLIL::Wire *wire;
|
|
union {
|
|
RTLIL::State data; // used if wire == NULL
|
|
int offset; // used if wire != NULL
|
|
};
|
|
|
|
SigBit();
|
|
SigBit(RTLIL::State bit);
|
|
explicit SigBit(bool bit);
|
|
SigBit(RTLIL::Wire *wire);
|
|
SigBit(RTLIL::Wire *wire, int offset);
|
|
SigBit(const RTLIL::SigChunk &chunk);
|
|
SigBit(const RTLIL::SigChunk &chunk, int index);
|
|
SigBit(const RTLIL::SigSpec &sig);
|
|
SigBit(const RTLIL::SigBit &sigbit) = default;
|
|
RTLIL::SigBit &operator =(const RTLIL::SigBit &other) = default;
|
|
|
|
inline bool is_wire() const { return wire != NULL; }
|
|
|
|
bool operator <(const RTLIL::SigBit &other) const;
|
|
bool operator ==(const RTLIL::SigBit &other) const;
|
|
bool operator !=(const RTLIL::SigBit &other) const;
|
|
unsigned int hash() const;
|
|
};
|
|
|
|
struct RTLIL::SigSpecIterator
|
|
{
|
|
typedef std::input_iterator_tag iterator_category;
|
|
typedef RTLIL::SigBit value_type;
|
|
typedef ptrdiff_t difference_type;
|
|
typedef RTLIL::SigBit* pointer;
|
|
typedef RTLIL::SigBit& reference;
|
|
|
|
RTLIL::SigSpec *sig_p;
|
|
int index;
|
|
|
|
inline RTLIL::SigBit &operator*() const;
|
|
inline bool operator!=(const RTLIL::SigSpecIterator &other) const { return index != other.index; }
|
|
inline bool operator==(const RTLIL::SigSpecIterator &other) const { return index == other.index; }
|
|
inline void operator++() { index++; }
|
|
};
|
|
|
|
struct RTLIL::SigSpecConstIterator
|
|
{
|
|
typedef std::input_iterator_tag iterator_category;
|
|
typedef RTLIL::SigBit value_type;
|
|
typedef ptrdiff_t difference_type;
|
|
typedef RTLIL::SigBit* pointer;
|
|
typedef RTLIL::SigBit& reference;
|
|
|
|
const RTLIL::SigSpec *sig_p;
|
|
int index;
|
|
|
|
inline const RTLIL::SigBit &operator*() const;
|
|
inline bool operator!=(const RTLIL::SigSpecConstIterator &other) const { return index != other.index; }
|
|
inline bool operator==(const RTLIL::SigSpecIterator &other) const { return index == other.index; }
|
|
inline void operator++() { index++; }
|
|
};
|
|
|
|
struct RTLIL::SigSpec
|
|
{
|
|
private:
|
|
int width_;
|
|
unsigned long hash_;
|
|
std::vector<RTLIL::SigChunk> chunks_; // LSB at index 0
|
|
std::vector<RTLIL::SigBit> bits_; // LSB at index 0
|
|
|
|
void pack() const;
|
|
void unpack() const;
|
|
void updhash() const;
|
|
|
|
inline bool packed() const {
|
|
return bits_.empty();
|
|
}
|
|
|
|
inline void inline_unpack() const {
|
|
if (!chunks_.empty())
|
|
unpack();
|
|
}
|
|
|
|
// Only used by Module::remove(const pool<Wire*> &wires)
|
|
// but cannot be more specific as it isn't yet declared
|
|
friend struct RTLIL::Module;
|
|
|
|
public:
|
|
SigSpec() : width_(0), hash_(0) {}
|
|
SigSpec(std::initializer_list<RTLIL::SigSpec> parts);
|
|
|
|
SigSpec(const RTLIL::Const &value);
|
|
SigSpec(RTLIL::Const &&value);
|
|
SigSpec(const RTLIL::SigChunk &chunk);
|
|
SigSpec(RTLIL::SigChunk &&chunk);
|
|
SigSpec(RTLIL::Wire *wire);
|
|
SigSpec(RTLIL::Wire *wire, int offset, int width = 1);
|
|
SigSpec(const std::string &str);
|
|
SigSpec(int val, int width = 32);
|
|
SigSpec(RTLIL::State bit, int width = 1);
|
|
SigSpec(const RTLIL::SigBit &bit, int width = 1);
|
|
SigSpec(const std::vector<RTLIL::SigChunk> &chunks);
|
|
SigSpec(const std::vector<RTLIL::SigBit> &bits);
|
|
SigSpec(const pool<RTLIL::SigBit> &bits);
|
|
SigSpec(const std::set<RTLIL::SigBit> &bits);
|
|
explicit SigSpec(bool bit);
|
|
|
|
size_t get_hash() const {
|
|
if (!hash_) hash();
|
|
return hash_;
|
|
}
|
|
|
|
inline const std::vector<RTLIL::SigChunk> &chunks() const { pack(); return chunks_; }
|
|
inline const std::vector<RTLIL::SigBit> &bits() const { inline_unpack(); return bits_; }
|
|
|
|
inline int size() const { return width_; }
|
|
inline bool empty() const { return width_ == 0; }
|
|
|
|
inline RTLIL::SigBit &operator[](int index) { inline_unpack(); return bits_.at(index); }
|
|
inline const RTLIL::SigBit &operator[](int index) const { inline_unpack(); return bits_.at(index); }
|
|
|
|
inline RTLIL::SigSpecIterator begin() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = 0; return it; }
|
|
inline RTLIL::SigSpecIterator end() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = width_; return it; }
|
|
|
|
inline RTLIL::SigSpecConstIterator begin() const { RTLIL::SigSpecConstIterator it; it.sig_p = this; it.index = 0; return it; }
|
|
inline RTLIL::SigSpecConstIterator end() const { RTLIL::SigSpecConstIterator it; it.sig_p = this; it.index = width_; return it; }
|
|
|
|
void sort();
|
|
void sort_and_unify();
|
|
|
|
void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with);
|
|
void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const;
|
|
|
|
void replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules);
|
|
void replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const;
|
|
|
|
void replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules);
|
|
void replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const;
|
|
|
|
void replace(int offset, const RTLIL::SigSpec &with);
|
|
|
|
void remove(const RTLIL::SigSpec &pattern);
|
|
void remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const;
|
|
void remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other);
|
|
|
|
void remove(const pool<RTLIL::SigBit> &pattern);
|
|
void remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const;
|
|
void remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other);
|
|
void remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other);
|
|
void remove2(const pool<RTLIL::Wire*> &pattern, RTLIL::SigSpec *other);
|
|
|
|
void remove(int offset, int length = 1);
|
|
void remove_const();
|
|
|
|
RTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other = NULL) const;
|
|
RTLIL::SigSpec extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other = NULL) const;
|
|
RTLIL::SigSpec extract(int offset, int length = 1) const;
|
|
RTLIL::SigSpec extract_end(int offset) const { return extract(offset, width_ - offset); }
|
|
|
|
RTLIL::SigBit lsb() const { log_assert(width_); return (*this)[0]; };
|
|
RTLIL::SigBit msb() const { log_assert(width_); return (*this)[width_ - 1]; };
|
|
|
|
void append(const RTLIL::SigSpec &signal);
|
|
inline void append(Wire *wire) { append(RTLIL::SigSpec(wire)); }
|
|
inline void append(const RTLIL::SigChunk &chunk) { append(RTLIL::SigSpec(chunk)); }
|
|
inline void append(const RTLIL::Const &const_) { append(RTLIL::SigSpec(const_)); }
|
|
|
|
void append(const RTLIL::SigBit &bit);
|
|
inline void append(RTLIL::State state) { append(RTLIL::SigBit(state)); }
|
|
inline void append(bool bool_) { append(RTLIL::SigBit(bool_)); }
|
|
|
|
void extend_u0(int width, bool is_signed = false);
|
|
|
|
RTLIL::SigSpec repeat(int num) const;
|
|
|
|
void reverse() { inline_unpack(); std::reverse(bits_.begin(), bits_.end()); }
|
|
|
|
bool operator <(const RTLIL::SigSpec &other) const;
|
|
bool operator ==(const RTLIL::SigSpec &other) const;
|
|
inline bool operator !=(const RTLIL::SigSpec &other) const { return !(*this == other); }
|
|
|
|
bool is_wire() const;
|
|
bool is_chunk() const;
|
|
inline bool is_bit() const { return width_ == 1; }
|
|
|
|
bool is_fully_const() const;
|
|
bool is_fully_zero() const;
|
|
bool is_fully_ones() const;
|
|
bool is_fully_def() const;
|
|
bool is_fully_undef() const;
|
|
bool has_const() const;
|
|
bool has_marked_bits() const;
|
|
bool is_onehot(int *pos = nullptr) const;
|
|
|
|
bool as_bool() const;
|
|
int as_int(bool is_signed = false) const;
|
|
std::string as_string() const;
|
|
RTLIL::Const as_const() const;
|
|
RTLIL::Wire *as_wire() const;
|
|
RTLIL::SigChunk as_chunk() const;
|
|
RTLIL::SigBit as_bit() const;
|
|
|
|
bool match(const char* pattern) const;
|
|
|
|
std::set<RTLIL::SigBit> to_sigbit_set() const;
|
|
pool<RTLIL::SigBit> to_sigbit_pool() const;
|
|
std::vector<RTLIL::SigBit> to_sigbit_vector() const;
|
|
std::map<RTLIL::SigBit, RTLIL::SigBit> to_sigbit_map(const RTLIL::SigSpec &other) const;
|
|
dict<RTLIL::SigBit, RTLIL::SigBit> to_sigbit_dict(const RTLIL::SigSpec &other) const;
|
|
|
|
static bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);
|
|
static bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str);
|
|
static bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);
|
|
|
|
operator std::vector<RTLIL::SigChunk>() const { return chunks(); }
|
|
operator std::vector<RTLIL::SigBit>() const { return bits(); }
|
|
const RTLIL::SigBit &at(int offset, const RTLIL::SigBit &defval) { return offset < width_ ? (*this)[offset] : defval; }
|
|
|
|
unsigned int hash() const { if (!hash_) updhash(); return hash_; };
|
|
|
|
#ifndef NDEBUG
|
|
void check(Module *mod = nullptr) const;
|
|
#else
|
|
void check(Module *mod = nullptr) const { (void)mod; }
|
|
#endif
|
|
};
|
|
|
|
struct RTLIL::Selection
|
|
{
|
|
bool full_selection;
|
|
pool<RTLIL::IdString> selected_modules;
|
|
dict<RTLIL::IdString, pool<RTLIL::IdString>> selected_members;
|
|
|
|
Selection(bool full = true) : full_selection(full) { }
|
|
|
|
bool selected_module(const RTLIL::IdString &mod_name) const;
|
|
bool selected_whole_module(const RTLIL::IdString &mod_name) const;
|
|
bool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const;
|
|
void optimize(RTLIL::Design *design);
|
|
|
|
template<typename T1> void select(T1 *module) {
|
|
if (!full_selection && selected_modules.count(module->name) == 0) {
|
|
selected_modules.insert(module->name);
|
|
selected_members.erase(module->name);
|
|
}
|
|
}
|
|
|
|
template<typename T1, typename T2> void select(T1 *module, T2 *member) {
|
|
if (!full_selection && selected_modules.count(module->name) == 0)
|
|
selected_members[module->name].insert(member->name);
|
|
}
|
|
|
|
bool empty() const {
|
|
return !full_selection && selected_modules.empty() && selected_members.empty();
|
|
}
|
|
};
|
|
|
|
struct RTLIL::Monitor
|
|
{
|
|
unsigned int hashidx_;
|
|
unsigned int hash() const { return hashidx_; }
|
|
|
|
Monitor() {
|
|
static unsigned int hashidx_count = 123456789;
|
|
hashidx_count = mkhash_xorshift(hashidx_count);
|
|
hashidx_ = hashidx_count;
|
|
}
|
|
|
|
virtual ~Monitor() { }
|
|
virtual void notify_module_add(RTLIL::Module*) { }
|
|
virtual void notify_module_del(RTLIL::Module*) { }
|
|
virtual void notify_connect(RTLIL::Cell*, const RTLIL::IdString&, const RTLIL::SigSpec&, const RTLIL::SigSpec&) { }
|
|
virtual void notify_connect(RTLIL::Module*, const RTLIL::SigSig&) { }
|
|
virtual void notify_connect(RTLIL::Module*, const std::vector<RTLIL::SigSig>&) { }
|
|
virtual void notify_blackout(RTLIL::Module*) { }
|
|
};
|
|
|
|
// Forward declaration; defined in preproc.h.
|
|
struct define_map_t;
|
|
|
|
struct RTLIL::Design
|
|
{
|
|
unsigned int hashidx_;
|
|
unsigned int hash() const { return hashidx_; }
|
|
|
|
pool<RTLIL::Monitor*> monitors;
|
|
dict<std::string, std::string> scratchpad;
|
|
|
|
bool flagBufferedNormalized = false;
|
|
void bufNormalize(bool enable=true);
|
|
|
|
int refcount_modules_;
|
|
dict<RTLIL::IdString, RTLIL::Module*> modules_;
|
|
std::vector<RTLIL::Binding*> bindings_;
|
|
|
|
std::vector<AST::AstNode*> verilog_packages, verilog_globals;
|
|
std::unique_ptr<define_map_t> verilog_defines;
|
|
|
|
std::vector<RTLIL::Selection> selection_stack;
|
|
dict<RTLIL::IdString, RTLIL::Selection> selection_vars;
|
|
std::string selected_active_module;
|
|
|
|
Design();
|
|
~Design();
|
|
|
|
RTLIL::ObjRange<RTLIL::Module*> modules();
|
|
RTLIL::Module *module(const RTLIL::IdString &name);
|
|
const RTLIL::Module *module(const RTLIL::IdString &name) const;
|
|
RTLIL::Module *top_module();
|
|
|
|
bool has(const RTLIL::IdString &id) const {
|
|
return modules_.count(id) != 0;
|
|
}
|
|
|
|
void add(RTLIL::Module *module);
|
|
void add(RTLIL::Binding *binding);
|
|
|
|
RTLIL::Module *addModule(RTLIL::IdString name);
|
|
void remove(RTLIL::Module *module);
|
|
void rename(RTLIL::Module *module, RTLIL::IdString new_name);
|
|
|
|
void scratchpad_unset(const std::string &varname);
|
|
|
|
void scratchpad_set_int(const std::string &varname, int value);
|
|
void scratchpad_set_bool(const std::string &varname, bool value);
|
|
void scratchpad_set_string(const std::string &varname, std::string value);
|
|
|
|
int scratchpad_get_int(const std::string &varname, int default_value = 0) const;
|
|
bool scratchpad_get_bool(const std::string &varname, bool default_value = false) const;
|
|
std::string scratchpad_get_string(const std::string &varname, const std::string &default_value = std::string()) const;
|
|
|
|
void sort();
|
|
void check();
|
|
void optimize();
|
|
|
|
bool selected_module(const RTLIL::IdString &mod_name) const;
|
|
bool selected_whole_module(const RTLIL::IdString &mod_name) const;
|
|
bool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const;
|
|
|
|
bool selected_module(RTLIL::Module *mod) const;
|
|
bool selected_whole_module(RTLIL::Module *mod) const;
|
|
|
|
RTLIL::Selection &selection() {
|
|
return selection_stack.back();
|
|
}
|
|
|
|
const RTLIL::Selection &selection() const {
|
|
return selection_stack.back();
|
|
}
|
|
|
|
bool full_selection() const {
|
|
return selection_stack.back().full_selection;
|
|
}
|
|
|
|
template<typename T1> bool selected(T1 *module) const {
|
|
return selected_module(module->name);
|
|
}
|
|
|
|
template<typename T1, typename T2> bool selected(T1 *module, T2 *member) const {
|
|
return selected_member(module->name, member->name);
|
|
}
|
|
|
|
template<typename T1> void select(T1 *module) {
|
|
if (selection_stack.size() > 0) {
|
|
RTLIL::Selection &sel = selection_stack.back();
|
|
sel.select(module);
|
|
}
|
|
}
|
|
|
|
template<typename T1, typename T2> void select(T1 *module, T2 *member) {
|
|
if (selection_stack.size() > 0) {
|
|
RTLIL::Selection &sel = selection_stack.back();
|
|
sel.select(module, member);
|
|
}
|
|
}
|
|
|
|
|
|
std::vector<RTLIL::Module*> selected_modules() const;
|
|
std::vector<RTLIL::Module*> selected_whole_modules() const;
|
|
std::vector<RTLIL::Module*> selected_whole_modules_warn(bool include_wb = false) const;
|
|
#ifdef WITH_PYTHON
|
|
static std::map<unsigned int, RTLIL::Design*> *get_all_designs(void);
|
|
#endif
|
|
};
|
|
|
|
struct RTLIL::Module : public RTLIL::AttrObject
|
|
{
|
|
unsigned int hashidx_;
|
|
unsigned int hash() const { return hashidx_; }
|
|
|
|
protected:
|
|
void add(RTLIL::Wire *wire);
|
|
void add(RTLIL::Cell *cell);
|
|
void add(RTLIL::Process *process);
|
|
|
|
public:
|
|
RTLIL::Design *design;
|
|
pool<RTLIL::Monitor*> monitors;
|
|
|
|
int refcount_wires_;
|
|
int refcount_cells_;
|
|
|
|
dict<RTLIL::IdString, RTLIL::Wire*> wires_;
|
|
dict<RTLIL::IdString, RTLIL::Cell*> cells_;
|
|
|
|
std::vector<RTLIL::SigSig> connections_;
|
|
std::vector<RTLIL::Binding*> bindings_;
|
|
|
|
RTLIL::IdString name;
|
|
idict<RTLIL::IdString> avail_parameters;
|
|
dict<RTLIL::IdString, RTLIL::Const> parameter_default_values;
|
|
dict<RTLIL::IdString, RTLIL::Memory*> memories;
|
|
dict<RTLIL::IdString, RTLIL::Process*> processes;
|
|
|
|
Module();
|
|
virtual ~Module();
|
|
virtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> ¶meters, bool mayfail = false);
|
|
virtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> ¶meters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail = false);
|
|
virtual size_t count_id(const RTLIL::IdString& id);
|
|
virtual void expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces);
|
|
virtual bool reprocess_if_necessary(RTLIL::Design *design);
|
|
|
|
virtual void sort();
|
|
virtual void check();
|
|
virtual void optimize();
|
|
virtual void makeblackbox();
|
|
|
|
void connect(const RTLIL::SigSig &conn);
|
|
void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);
|
|
void new_connections(const std::vector<RTLIL::SigSig> &new_conn);
|
|
const std::vector<RTLIL::SigSig> &connections() const;
|
|
|
|
std::vector<RTLIL::IdString> ports;
|
|
void fixup_ports();
|
|
|
|
pool<pair<RTLIL::Cell*, RTLIL::IdString>> bufNormQueue;
|
|
void bufNormalize();
|
|
|
|
template<typename T> void rewrite_sigspecs(T &functor);
|
|
template<typename T> void rewrite_sigspecs2(T &functor);
|
|
void cloneInto(RTLIL::Module *new_mod) const;
|
|
virtual RTLIL::Module *clone() const;
|
|
|
|
bool has_memories() const;
|
|
bool has_processes() const;
|
|
|
|
bool has_memories_warn() const;
|
|
bool has_processes_warn() const;
|
|
|
|
std::vector<RTLIL::Wire*> selected_wires() const;
|
|
std::vector<RTLIL::Cell*> selected_cells() const;
|
|
|
|
template<typename T> bool selected(T *member) const {
|
|
return design->selected_member(name, member->name);
|
|
}
|
|
|
|
RTLIL::Wire* wire(const RTLIL::IdString &id) {
|
|
auto it = wires_.find(id);
|
|
return it == wires_.end() ? nullptr : it->second;
|
|
}
|
|
RTLIL::Cell* cell(const RTLIL::IdString &id) {
|
|
auto it = cells_.find(id);
|
|
return it == cells_.end() ? nullptr : it->second;
|
|
}
|
|
|
|
const RTLIL::Wire* wire(const RTLIL::IdString &id) const{
|
|
auto it = wires_.find(id);
|
|
return it == wires_.end() ? nullptr : it->second;
|
|
}
|
|
const RTLIL::Cell* cell(const RTLIL::IdString &id) const {
|
|
auto it = cells_.find(id);
|
|
return it == cells_.end() ? nullptr : it->second;
|
|
}
|
|
|
|
RTLIL::ObjRange<RTLIL::Wire*> wires() { return RTLIL::ObjRange<RTLIL::Wire*>(&wires_, &refcount_wires_); }
|
|
RTLIL::ObjRange<RTLIL::Cell*> cells() { return RTLIL::ObjRange<RTLIL::Cell*>(&cells_, &refcount_cells_); }
|
|
|
|
void add(RTLIL::Binding *binding);
|
|
|
|
// Removing wires is expensive. If you have to remove wires, remove them all at once.
|
|
void remove(const pool<RTLIL::Wire*> &wires);
|
|
void remove(RTLIL::Cell *cell);
|
|
void remove(RTLIL::Process *process);
|
|
|
|
void rename(RTLIL::Wire *wire, RTLIL::IdString new_name);
|
|
void rename(RTLIL::Cell *cell, RTLIL::IdString new_name);
|
|
void rename(RTLIL::IdString old_name, RTLIL::IdString new_name);
|
|
|
|
void swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2);
|
|
void swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2);
|
|
|
|
RTLIL::IdString uniquify(RTLIL::IdString name);
|
|
RTLIL::IdString uniquify(RTLIL::IdString name, int &index);
|
|
|
|
RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);
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RTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other);
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RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type);
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RTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other);
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RTLIL::Memory *addMemory(RTLIL::IdString name, const RTLIL::Memory *other);
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RTLIL::Process *addProcess(RTLIL::IdString name);
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RTLIL::Process *addProcess(RTLIL::IdString name, const RTLIL::Process *other);
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// The add* methods create a cell and return the created cell. All signals must exist in advance.
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RTLIL::Cell* addNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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RTLIL::Cell* addPos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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RTLIL::Cell* addBuf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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RTLIL::Cell* addNeg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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RTLIL::Cell* addAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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RTLIL::Cell* addOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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RTLIL::Cell* addXor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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RTLIL::Cell* addXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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RTLIL::Cell* addReduceAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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RTLIL::Cell* addReduceOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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RTLIL::Cell* addReduceXor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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RTLIL::Cell* addReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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RTLIL::Cell* addReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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RTLIL::Cell* addShl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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RTLIL::Cell* addShr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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RTLIL::Cell* addSshl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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RTLIL::Cell* addSshr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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RTLIL::Cell* addShift (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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RTLIL::Cell* addShiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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RTLIL::Cell* addLt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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RTLIL::Cell* addLe (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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RTLIL::Cell* addEq (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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RTLIL::Cell* addNe (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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RTLIL::Cell* addEqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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RTLIL::Cell* addNex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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RTLIL::Cell* addGe (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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RTLIL::Cell* addGt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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RTLIL::Cell* addAdd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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RTLIL::Cell* addSub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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RTLIL::Cell* addMul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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// truncating division
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RTLIL::Cell* addDiv (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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// truncating modulo
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RTLIL::Cell* addMod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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RTLIL::Cell* addDivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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RTLIL::Cell* addModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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RTLIL::Cell* addPow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed = false, bool b_signed = false, const std::string &src = "");
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RTLIL::Cell* addFa (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_x, const RTLIL::SigSpec &sig_y, const std::string &src = "");
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RTLIL::Cell* addLogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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RTLIL::Cell* addLogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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RTLIL::Cell* addLogicOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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RTLIL::Cell* addMux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = "");
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RTLIL::Cell* addPmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = "");
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RTLIL::Cell* addBmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = "");
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RTLIL::Cell* addDemux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = "");
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RTLIL::Cell* addBweqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = "");
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RTLIL::Cell* addBwmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = "");
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RTLIL::Cell* addSlice (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const std::string &src = "");
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RTLIL::Cell* addConcat (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = "");
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RTLIL::Cell* addLut (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, const std::string &src = "");
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RTLIL::Cell* addTribuf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, const std::string &src = "");
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RTLIL::Cell* addAssert (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = "");
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RTLIL::Cell* addAssume (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = "");
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RTLIL::Cell* addLive (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = "");
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RTLIL::Cell* addFair (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = "");
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RTLIL::Cell* addCover (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = "");
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RTLIL::Cell* addEquiv (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = "");
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RTLIL::Cell* addSr (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = "");
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RTLIL::Cell* addFf (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = "");
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RTLIL::Cell* addDff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, const std::string &src = "");
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RTLIL::Cell* addDffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = "");
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RTLIL::Cell* addDffsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = "");
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RTLIL::Cell* addDffsre (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = "");
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RTLIL::Cell* addAdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = "");
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RTLIL::Cell* addAdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, const std::string &src = "");
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RTLIL::Cell* addAldff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, const std::string &src = "");
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RTLIL::Cell* addAldffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, const std::string &src = "");
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RTLIL::Cell* addSdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool srst_polarity = true, const std::string &src = "");
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RTLIL::Cell* addSdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = "");
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RTLIL::Cell* addSdffce (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = "");
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RTLIL::Cell* addDlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, const std::string &src = "");
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RTLIL::Cell* addAdlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool en_polarity = true, bool arst_polarity = true, const std::string &src = "");
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RTLIL::Cell* addDlatchsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = "");
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RTLIL::Cell* addBufGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, const std::string &src = "");
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RTLIL::Cell* addNotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, const std::string &src = "");
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RTLIL::Cell* addAndGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = "");
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RTLIL::Cell* addNandGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = "");
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RTLIL::Cell* addOrGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = "");
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RTLIL::Cell* addNorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = "");
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RTLIL::Cell* addXorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = "");
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RTLIL::Cell* addXnorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = "");
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RTLIL::Cell* addAndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = "");
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RTLIL::Cell* addOrnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = "");
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RTLIL::Cell* addMuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, const std::string &src = "");
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RTLIL::Cell* addNmuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, const std::string &src = "");
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RTLIL::Cell* addAoi3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, const std::string &src = "");
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RTLIL::Cell* addOai3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, const std::string &src = "");
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RTLIL::Cell* addAoi4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, const std::string &src = "");
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RTLIL::Cell* addOai4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, const std::string &src = "");
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RTLIL::Cell* addSrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
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const RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = "");
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RTLIL::Cell* addFfGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = "");
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RTLIL::Cell* addDffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, const std::string &src = "");
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RTLIL::Cell* addDffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = "");
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RTLIL::Cell* addDffsrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
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RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = "");
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RTLIL::Cell* addDffsreGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
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RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = "");
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RTLIL::Cell* addAdffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
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bool arst_value = false, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = "");
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RTLIL::Cell* addAdffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
|
|
bool arst_value = false, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, const std::string &src = "");
|
|
RTLIL::Cell* addAldffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
|
|
const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, const std::string &src = "");
|
|
RTLIL::Cell* addAldffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
|
|
const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, const std::string &src = "");
|
|
RTLIL::Cell* addSdffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
|
|
bool srst_value = false, bool clk_polarity = true, bool srst_polarity = true, const std::string &src = "");
|
|
RTLIL::Cell* addSdffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
|
|
bool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = "");
|
|
RTLIL::Cell* addSdffceGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
|
|
bool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = "");
|
|
RTLIL::Cell* addDlatchGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, const std::string &src = "");
|
|
RTLIL::Cell* addAdlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
|
|
bool arst_value = false, bool en_polarity = true, bool arst_polarity = true, const std::string &src = "");
|
|
RTLIL::Cell* addDlatchsrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
|
|
RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = "");
|
|
|
|
RTLIL::Cell* addAnyinit(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = "");
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|
|
|
// The methods without the add* prefix create a cell and an output signal. They return the newly created output signal.
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|
|
|
RTLIL::SigSpec Not (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = "");
|
|
RTLIL::SigSpec Pos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = "");
|
|
RTLIL::SigSpec Buf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = "");
|
|
RTLIL::SigSpec Neg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = "");
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|
|
|
RTLIL::SigSpec And (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = "");
|
|
RTLIL::SigSpec Or (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = "");
|
|
RTLIL::SigSpec Xor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = "");
|
|
RTLIL::SigSpec Xnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = "");
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|
|
|
RTLIL::SigSpec ReduceAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = "");
|
|
RTLIL::SigSpec ReduceOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = "");
|
|
RTLIL::SigSpec ReduceXor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = "");
|
|
RTLIL::SigSpec ReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = "");
|
|
RTLIL::SigSpec ReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = "");
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|
|
|
RTLIL::SigSpec Shl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = "");
|
|
RTLIL::SigSpec Shr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = "");
|
|
RTLIL::SigSpec Sshl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = "");
|
|
RTLIL::SigSpec Sshr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = "");
|
|
RTLIL::SigSpec Shift (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = "");
|
|
RTLIL::SigSpec Shiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = "");
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|
|
|
RTLIL::SigSpec Lt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = "");
|
|
RTLIL::SigSpec Le (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = "");
|
|
RTLIL::SigSpec Eq (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = "");
|
|
RTLIL::SigSpec Ne (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = "");
|
|
RTLIL::SigSpec Eqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = "");
|
|
RTLIL::SigSpec Nex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = "");
|
|
RTLIL::SigSpec Ge (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = "");
|
|
RTLIL::SigSpec Gt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = "");
|
|
|
|
RTLIL::SigSpec Add (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = "");
|
|
RTLIL::SigSpec Sub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = "");
|
|
RTLIL::SigSpec Mul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = "");
|
|
// truncating division
|
|
RTLIL::SigSpec Div (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = "");
|
|
// truncating modulo
|
|
RTLIL::SigSpec Mod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = "");
|
|
RTLIL::SigSpec DivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = "");
|
|
RTLIL::SigSpec ModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = "");
|
|
RTLIL::SigSpec Pow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool a_signed = false, bool b_signed = false, const std::string &src = "");
|
|
|
|
RTLIL::SigSpec LogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = "");
|
|
RTLIL::SigSpec LogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = "");
|
|
RTLIL::SigSpec LogicOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = "");
|
|
|
|
RTLIL::SigSpec Mux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = "");
|
|
RTLIL::SigSpec Pmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = "");
|
|
RTLIL::SigSpec Bmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const std::string &src = "");
|
|
RTLIL::SigSpec Demux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const std::string &src = "");
|
|
|
|
RTLIL::SigSpec Bweqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const std::string &src = "");
|
|
RTLIL::SigSpec Bwmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = "");
|
|
|
|
RTLIL::SigBit BufGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const std::string &src = "");
|
|
RTLIL::SigBit NotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const std::string &src = "");
|
|
RTLIL::SigBit AndGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = "");
|
|
RTLIL::SigBit NandGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = "");
|
|
RTLIL::SigBit OrGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = "");
|
|
RTLIL::SigBit NorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = "");
|
|
RTLIL::SigBit XorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = "");
|
|
RTLIL::SigBit XnorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = "");
|
|
RTLIL::SigBit AndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = "");
|
|
RTLIL::SigBit OrnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = "");
|
|
RTLIL::SigBit MuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const std::string &src = "");
|
|
RTLIL::SigBit NmuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const std::string &src = "");
|
|
RTLIL::SigBit Aoi3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const std::string &src = "");
|
|
RTLIL::SigBit Oai3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const std::string &src = "");
|
|
RTLIL::SigBit Aoi4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const std::string &src = "");
|
|
RTLIL::SigBit Oai4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const std::string &src = "");
|
|
|
|
RTLIL::SigSpec Anyconst (RTLIL::IdString name, int width = 1, const std::string &src = "");
|
|
RTLIL::SigSpec Anyseq (RTLIL::IdString name, int width = 1, const std::string &src = "");
|
|
RTLIL::SigSpec Allconst (RTLIL::IdString name, int width = 1, const std::string &src = "");
|
|
RTLIL::SigSpec Allseq (RTLIL::IdString name, int width = 1, const std::string &src = "");
|
|
RTLIL::SigSpec Initstate (RTLIL::IdString name, const std::string &src = "");
|
|
|
|
RTLIL::SigSpec SetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src = "");
|
|
RTLIL::Cell* addSetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_y, const std::string &src = "");
|
|
RTLIL::SigSpec GetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = "");
|
|
RTLIL::Cell* addOverwriteTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src = "");
|
|
RTLIL::SigSpec OriginalTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = "");
|
|
RTLIL::SigSpec FutureFF (RTLIL::IdString name, const RTLIL::SigSpec &sig_e, const std::string &src = "");
|
|
|
|
#ifdef WITH_PYTHON
|
|
static std::map<unsigned int, RTLIL::Module*> *get_all_modules(void);
|
|
#endif
|
|
};
|
|
|
|
namespace RTLIL_BACKEND {
|
|
void dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire);
|
|
}
|
|
|
|
struct RTLIL::Wire : public RTLIL::AttrObject
|
|
{
|
|
unsigned int hashidx_;
|
|
unsigned int hash() const { return hashidx_; }
|
|
|
|
protected:
|
|
// use module->addWire() and module->remove() to create or destroy wires
|
|
friend struct RTLIL::Module;
|
|
Wire();
|
|
~Wire();
|
|
|
|
friend struct RTLIL::Design;
|
|
friend struct RTLIL::Cell;
|
|
friend void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire);
|
|
RTLIL::Cell *driverCell_ = nullptr;
|
|
RTLIL::IdString driverPort_;
|
|
|
|
public:
|
|
// do not simply copy wires
|
|
Wire(RTLIL::Wire &other) = delete;
|
|
void operator=(RTLIL::Wire &other) = delete;
|
|
|
|
RTLIL::Module *module;
|
|
RTLIL::IdString name;
|
|
int width, start_offset, port_id;
|
|
bool port_input, port_output, upto, is_signed;
|
|
|
|
RTLIL::Cell *driverCell() const { log_assert(driverCell_); return driverCell_; };
|
|
RTLIL::IdString driverPort() const { log_assert(driverCell_); return driverPort_; };
|
|
|
|
#ifdef WITH_PYTHON
|
|
static std::map<unsigned int, RTLIL::Wire*> *get_all_wires(void);
|
|
#endif
|
|
};
|
|
|
|
inline int GetSize(RTLIL::Wire *wire) {
|
|
return wire->width;
|
|
}
|
|
|
|
struct RTLIL::Memory : public RTLIL::AttrObject
|
|
{
|
|
unsigned int hashidx_;
|
|
unsigned int hash() const { return hashidx_; }
|
|
|
|
Memory();
|
|
|
|
RTLIL::IdString name;
|
|
int width, start_offset, size;
|
|
#ifdef WITH_PYTHON
|
|
~Memory();
|
|
static std::map<unsigned int, RTLIL::Memory*> *get_all_memorys(void);
|
|
#endif
|
|
};
|
|
|
|
struct RTLIL::Cell : public RTLIL::AttrObject
|
|
{
|
|
unsigned int hashidx_;
|
|
unsigned int hash() const { return hashidx_; }
|
|
|
|
protected:
|
|
// use module->addCell() and module->remove() to create or destroy cells
|
|
friend struct RTLIL::Module;
|
|
Cell();
|
|
~Cell();
|
|
|
|
public:
|
|
// do not simply copy cells
|
|
Cell(RTLIL::Cell &other) = delete;
|
|
void operator=(RTLIL::Cell &other) = delete;
|
|
|
|
RTLIL::Module *module;
|
|
RTLIL::IdString name;
|
|
RTLIL::IdString type;
|
|
dict<RTLIL::IdString, RTLIL::SigSpec> connections_;
|
|
dict<RTLIL::IdString, RTLIL::Const> parameters;
|
|
|
|
// access cell ports
|
|
bool hasPort(const RTLIL::IdString &portname) const;
|
|
void unsetPort(const RTLIL::IdString &portname);
|
|
void setPort(const RTLIL::IdString &portname, RTLIL::SigSpec signal);
|
|
const RTLIL::SigSpec &getPort(const RTLIL::IdString &portname) const;
|
|
const dict<RTLIL::IdString, RTLIL::SigSpec> &connections() const;
|
|
|
|
// information about cell ports
|
|
bool known() const;
|
|
bool input(const RTLIL::IdString &portname) const;
|
|
bool output(const RTLIL::IdString &portname) const;
|
|
|
|
// access cell parameters
|
|
bool hasParam(const RTLIL::IdString ¶mname) const;
|
|
void unsetParam(const RTLIL::IdString ¶mname);
|
|
void setParam(const RTLIL::IdString ¶mname, RTLIL::Const value);
|
|
const RTLIL::Const &getParam(const RTLIL::IdString ¶mname) const;
|
|
|
|
void sort();
|
|
void check();
|
|
void fixup_parameters(bool set_a_signed = false, bool set_b_signed = false);
|
|
|
|
bool has_keep_attr() const {
|
|
return get_bool_attribute(ID::keep) || (module && module->design && module->design->module(type) &&
|
|
module->design->module(type)->get_bool_attribute(ID::keep));
|
|
}
|
|
|
|
template<typename T> void rewrite_sigspecs(T &functor);
|
|
template<typename T> void rewrite_sigspecs2(T &functor);
|
|
|
|
#ifdef WITH_PYTHON
|
|
static std::map<unsigned int, RTLIL::Cell*> *get_all_cells(void);
|
|
#endif
|
|
|
|
bool has_memid() const;
|
|
bool is_mem_cell() const;
|
|
};
|
|
|
|
struct RTLIL::CaseRule : public RTLIL::AttrObject
|
|
{
|
|
std::vector<RTLIL::SigSpec> compare;
|
|
std::vector<RTLIL::SigSig> actions;
|
|
std::vector<RTLIL::SwitchRule*> switches;
|
|
|
|
~CaseRule();
|
|
|
|
bool empty() const;
|
|
|
|
template<typename T> void rewrite_sigspecs(T &functor);
|
|
template<typename T> void rewrite_sigspecs2(T &functor);
|
|
RTLIL::CaseRule *clone() const;
|
|
};
|
|
|
|
struct RTLIL::SwitchRule : public RTLIL::AttrObject
|
|
{
|
|
RTLIL::SigSpec signal;
|
|
std::vector<RTLIL::CaseRule*> cases;
|
|
|
|
~SwitchRule();
|
|
|
|
bool empty() const;
|
|
|
|
template<typename T> void rewrite_sigspecs(T &functor);
|
|
template<typename T> void rewrite_sigspecs2(T &functor);
|
|
RTLIL::SwitchRule *clone() const;
|
|
};
|
|
|
|
struct RTLIL::MemWriteAction : RTLIL::AttrObject
|
|
{
|
|
RTLIL::IdString memid;
|
|
RTLIL::SigSpec address;
|
|
RTLIL::SigSpec data;
|
|
RTLIL::SigSpec enable;
|
|
RTLIL::Const priority_mask;
|
|
};
|
|
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struct RTLIL::SyncRule
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{
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RTLIL::SyncType type;
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RTLIL::SigSpec signal;
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std::vector<RTLIL::SigSig> actions;
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std::vector<RTLIL::MemWriteAction> mem_write_actions;
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template<typename T> void rewrite_sigspecs(T &functor);
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template<typename T> void rewrite_sigspecs2(T &functor);
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RTLIL::SyncRule *clone() const;
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};
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struct RTLIL::Process : public RTLIL::AttrObject
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{
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unsigned int hashidx_;
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unsigned int hash() const { return hashidx_; }
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protected:
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// use module->addProcess() and module->remove() to create or destroy processes
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friend struct RTLIL::Module;
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Process();
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~Process();
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public:
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RTLIL::IdString name;
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RTLIL::Module *module;
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RTLIL::CaseRule root_case;
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std::vector<RTLIL::SyncRule*> syncs;
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template<typename T> void rewrite_sigspecs(T &functor);
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template<typename T> void rewrite_sigspecs2(T &functor);
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RTLIL::Process *clone() const;
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};
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inline RTLIL::SigBit::SigBit() : wire(NULL), data(RTLIL::State::S0) { }
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inline RTLIL::SigBit::SigBit(RTLIL::State bit) : wire(NULL), data(bit) { }
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inline RTLIL::SigBit::SigBit(bool bit) : wire(NULL), data(bit ? State::S1 : State::S0) { }
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inline RTLIL::SigBit::SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_assert(wire && wire->width == 1); }
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inline RTLIL::SigBit::SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire != nullptr); }
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inline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; }
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inline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data[index]; }
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inline bool RTLIL::SigBit::operator<(const RTLIL::SigBit &other) const {
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if (wire == other.wire)
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return wire ? (offset < other.offset) : (data < other.data);
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if (wire != nullptr && other.wire != nullptr)
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return wire->name < other.wire->name;
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return (wire != nullptr) < (other.wire != nullptr);
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}
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inline bool RTLIL::SigBit::operator==(const RTLIL::SigBit &other) const {
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return (wire == other.wire) && (wire ? (offset == other.offset) : (data == other.data));
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}
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inline bool RTLIL::SigBit::operator!=(const RTLIL::SigBit &other) const {
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return (wire != other.wire) || (wire ? (offset != other.offset) : (data != other.data));
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}
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inline unsigned int RTLIL::SigBit::hash() const {
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if (wire)
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return mkhash_add(wire->name.hash(), offset);
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return data;
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}
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inline RTLIL::SigBit &RTLIL::SigSpecIterator::operator*() const {
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return (*sig_p)[index];
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}
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inline const RTLIL::SigBit &RTLIL::SigSpecConstIterator::operator*() const {
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return (*sig_p)[index];
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}
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inline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) {
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log_assert(sig.size() == 1 && sig.chunks().size() == 1);
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*this = SigBit(sig.chunks().front());
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}
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template<typename T>
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void RTLIL::Module::rewrite_sigspecs(T &functor)
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{
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for (auto &it : cells_)
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it.second->rewrite_sigspecs(functor);
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for (auto &it : processes)
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it.second->rewrite_sigspecs(functor);
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for (auto &it : connections_) {
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functor(it.first);
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functor(it.second);
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}
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}
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template<typename T>
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void RTLIL::Module::rewrite_sigspecs2(T &functor)
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{
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for (auto &it : cells_)
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it.second->rewrite_sigspecs2(functor);
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for (auto &it : processes)
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it.second->rewrite_sigspecs2(functor);
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for (auto &it : connections_) {
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functor(it.first, it.second);
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}
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}
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template<typename T>
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void RTLIL::Cell::rewrite_sigspecs(T &functor) {
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for (auto &it : connections_)
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functor(it.second);
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}
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template<typename T>
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void RTLIL::Cell::rewrite_sigspecs2(T &functor) {
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for (auto &it : connections_)
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functor(it.second);
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}
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template<typename T>
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void RTLIL::CaseRule::rewrite_sigspecs(T &functor) {
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for (auto &it : compare)
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functor(it);
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for (auto &it : actions) {
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functor(it.first);
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functor(it.second);
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}
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for (auto it : switches)
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it->rewrite_sigspecs(functor);
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}
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template<typename T>
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void RTLIL::CaseRule::rewrite_sigspecs2(T &functor) {
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for (auto &it : compare)
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functor(it);
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for (auto &it : actions) {
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functor(it.first, it.second);
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}
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for (auto it : switches)
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it->rewrite_sigspecs2(functor);
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}
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template<typename T>
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void RTLIL::SwitchRule::rewrite_sigspecs(T &functor)
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{
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functor(signal);
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for (auto it : cases)
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it->rewrite_sigspecs(functor);
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}
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template<typename T>
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void RTLIL::SwitchRule::rewrite_sigspecs2(T &functor)
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{
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functor(signal);
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for (auto it : cases)
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it->rewrite_sigspecs2(functor);
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}
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template<typename T>
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void RTLIL::SyncRule::rewrite_sigspecs(T &functor)
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{
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functor(signal);
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for (auto &it : actions) {
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functor(it.first);
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functor(it.second);
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}
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for (auto &it : mem_write_actions) {
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functor(it.address);
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functor(it.data);
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functor(it.enable);
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}
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}
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template<typename T>
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void RTLIL::SyncRule::rewrite_sigspecs2(T &functor)
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{
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functor(signal);
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for (auto &it : actions) {
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functor(it.first, it.second);
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}
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for (auto &it : mem_write_actions) {
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functor(it.address);
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functor(it.data);
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functor(it.enable);
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}
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}
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template<typename T>
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void RTLIL::Process::rewrite_sigspecs(T &functor)
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{
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root_case.rewrite_sigspecs(functor);
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for (auto it : syncs)
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it->rewrite_sigspecs(functor);
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}
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template<typename T>
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void RTLIL::Process::rewrite_sigspecs2(T &functor)
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{
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root_case.rewrite_sigspecs2(functor);
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for (auto it : syncs)
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it->rewrite_sigspecs2(functor);
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}
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YOSYS_NAMESPACE_END
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#endif
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