mirror of https://github.com/YosysHQ/yosys.git
472 lines
14 KiB
C++
472 lines
14 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/celledges.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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void bitwise_unary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
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{
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bool is_signed = (cell->type != ID($buf)) && cell->getParam(ID::A_SIGNED).as_bool();
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int a_width = GetSize(cell->getPort(ID::A));
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int y_width = GetSize(cell->getPort(ID::Y));
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for (int i = 0; i < y_width; i++)
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{
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if (i < a_width)
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db->add_edge(cell, ID::A, i, ID::Y, i, -1);
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else if (is_signed && a_width > 0)
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db->add_edge(cell, ID::A, a_width-1, ID::Y, i, -1);
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}
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}
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void bitwise_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
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{
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bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
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int a_width = GetSize(cell->getPort(ID::A));
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int b_width = GetSize(cell->getPort(ID::B));
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int y_width = GetSize(cell->getPort(ID::Y));
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if (cell->type == ID($and) && !is_signed) {
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if (a_width > b_width)
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a_width = b_width;
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else
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b_width = a_width;
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}
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for (int i = 0; i < y_width; i++)
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{
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if (i < a_width)
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db->add_edge(cell, ID::A, i, ID::Y, i, -1);
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else if (is_signed && a_width > 0)
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db->add_edge(cell, ID::A, a_width-1, ID::Y, i, -1);
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if (i < b_width)
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db->add_edge(cell, ID::B, i, ID::Y, i, -1);
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else if (is_signed && b_width > 0)
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db->add_edge(cell, ID::B, b_width-1, ID::Y, i, -1);
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}
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}
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void arith_neg_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
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{
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bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
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int a_width = GetSize(cell->getPort(ID::A));
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int y_width = GetSize(cell->getPort(ID::Y));
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if (is_signed && a_width == 1)
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y_width = std::min(y_width, 1);
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for (int i = 0; i < y_width; i++)
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for (int k = 0; k <= i && k < a_width; k++)
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db->add_edge(cell, ID::A, k, ID::Y, i, -1);
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}
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void arith_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
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{
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bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
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int a_width = GetSize(cell->getPort(ID::A));
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int b_width = GetSize(cell->getPort(ID::B));
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int y_width = GetSize(cell->getPort(ID::Y));
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if (!is_signed && cell->type != ID($sub)) {
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int ab_width = std::max(a_width, b_width);
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y_width = std::min(y_width, ab_width+1);
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}
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for (int i = 0; i < y_width; i++)
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{
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for (int k = 0; k <= i; k++)
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{
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if (k < a_width)
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db->add_edge(cell, ID::A, k, ID::Y, i, -1);
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if (k < b_width)
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db->add_edge(cell, ID::B, k, ID::Y, i, -1);
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}
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}
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}
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void reduce_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
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{
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int a_width = GetSize(cell->getPort(ID::A));
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for (int i = 0; i < a_width; i++)
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db->add_edge(cell, ID::A, i, ID::Y, 0, -1);
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}
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void compare_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
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{
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int a_width = GetSize(cell->getPort(ID::A));
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int b_width = GetSize(cell->getPort(ID::B));
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for (int i = 0; i < a_width; i++)
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db->add_edge(cell, ID::A, i, ID::Y, 0, -1);
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for (int i = 0; i < b_width; i++)
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db->add_edge(cell, ID::B, i, ID::Y, 0, -1);
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}
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void mux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
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{
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int a_width = GetSize(cell->getPort(ID::A));
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int b_width = GetSize(cell->getPort(ID::B));
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int s_width = GetSize(cell->getPort(ID::S));
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for (int i = 0; i < a_width; i++)
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{
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db->add_edge(cell, ID::A, i, ID::Y, i, -1);
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for (int k = i; k < b_width; k += a_width)
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db->add_edge(cell, ID::B, k, ID::Y, i, -1);
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for (int k = 0; k < s_width; k++)
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db->add_edge(cell, ID::S, k, ID::Y, i, -1);
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}
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}
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void bmux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
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{
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int width = GetSize(cell->getPort(ID::Y));
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int a_width = GetSize(cell->getPort(ID::A));
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int s_width = GetSize(cell->getPort(ID::S));
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for (int i = 0; i < width; i++)
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{
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for (int k = i; k < a_width; k += width)
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db->add_edge(cell, ID::A, k, ID::Y, i, -1);
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for (int k = 0; k < s_width; k++)
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db->add_edge(cell, ID::S, k, ID::Y, i, -1);
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}
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}
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void demux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
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{
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int width = GetSize(cell->getPort(ID::Y));
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int a_width = GetSize(cell->getPort(ID::A));
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int s_width = GetSize(cell->getPort(ID::S));
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for (int i = 0; i < width; i++)
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{
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db->add_edge(cell, ID::A, i % a_width, ID::Y, i, -1);
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for (int k = 0; k < s_width; k++)
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db->add_edge(cell, ID::S, k, ID::Y, i, -1);
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}
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}
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void shift_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
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{
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bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
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bool is_b_signed = cell->getParam(ID::B_SIGNED).as_bool();
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int a_width = GetSize(cell->getPort(ID::A));
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int b_width = GetSize(cell->getPort(ID::B));
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int y_width = GetSize(cell->getPort(ID::Y));
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// Behavior of the different shift cells:
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//
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// $shl, $sshl -- shifts left by the amount on B port, B always unsigned
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// $shr, $sshr -- ditto right
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// $shift, $shiftx -- shifts right by the amount on B port, B optionally signed
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//
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// Sign extension (if A signed):
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//
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// $shl, $shr, $shift -- only sign-extends up to size of Y, then shifts in zeroes
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// $sshl, $sshr -- fully sign-extends
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// $shiftx -- no sign extension
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//
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// Because $shl, $sshl only shift left, and $shl sign-extens up to size of Y, they
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// are effectively the same.
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// the cap below makes sure we don't overflow in the arithmetic further down, though
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// it makes the edge data invalid once a_width approaches the order of 2**30
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// (that ever happening is considered improbable)
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int b_width_capped = min(b_width, 30);
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int b_high, b_low;
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if (!is_b_signed) {
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b_high = (1 << b_width_capped) - 1;
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b_low = 0;
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} else {
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b_high = (1 << (b_width_capped - 1)) - 1;
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b_low = -(1 << (b_width_capped - 1));
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}
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for (int i = 0; i < y_width; i++){
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// highest position of Y that can change with the value of B
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int b_range_upper = 0;
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// 1 + highest position of A that can be moved to Y[i]
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int a_range_upper;
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// lowest position of A that can be moved to Y[i]
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int a_range_lower;
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if (cell->type.in(ID($shl), ID($sshl))) {
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b_range_upper = a_width + b_high;
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if (is_signed) b_range_upper -= 1;
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a_range_lower = max(0, i - b_high);
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a_range_upper = min(i+1, a_width);
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} else if (cell->type.in(ID($shr), ID($sshr)) || (cell->type.in(ID($shift), ID($shiftx)) && !is_b_signed)) {
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b_range_upper = a_width;
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a_range_lower = min(i, a_width - 1);
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a_range_upper = min(i+1 + b_high, a_width);
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} else if (cell->type.in(ID($shift), ID($shiftx)) && is_b_signed) {
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// can go both ways depending on sign of B
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// 2's complement range is different depending on direction
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b_range_upper = a_width - b_low;
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a_range_lower = max(0, i + b_low);
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if (is_signed)
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a_range_lower = min(a_range_lower, a_width - 1);
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a_range_upper = min(i+1 + b_high, a_width);
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} else {
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log_assert(false && "unreachable");
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}
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if (i < b_range_upper) {
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for (int k = a_range_lower; k < a_range_upper; k++)
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db->add_edge(cell, ID::A, k, ID::Y, i, -1);
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} else {
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// only influence is through sign extension
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if (is_signed)
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db->add_edge(cell, ID::A, a_width - 1, ID::Y, i, -1);
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}
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for (int k = 0; k < b_width; k++) {
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// left shifts
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if (cell->type.in(ID($shl), ID($sshl))) {
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if (a_width == 1 && is_signed) {
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int skip = 1 << (k + 1);
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int base = skip -1;
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if (i % skip != base && i - a_width + 2 < 1 << b_width)
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db->add_edge(cell, ID::B, k, ID::Y, i, -1);
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} else if (is_signed) {
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if (i - a_width + 2 < 1 << b_width)
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db->add_edge(cell, ID::B, k, ID::Y, i, -1);
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} else {
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if (i - a_width + 1 < 1 << b_width)
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db->add_edge(cell, ID::B, k, ID::Y, i, -1);
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}
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// right shifts
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} else if (cell->type.in(ID($shr), ID($sshr)) || (cell->type.in(ID($shift), ID($shiftx)) && !is_b_signed)) {
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if (is_signed) {
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bool shift_in_bulk = i < a_width - 1;
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// can we jump into the zero-padding by toggling B[k]?
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bool zpad_jump = (((y_width - i) & ((1 << (k + 1)) - 1)) != 0 \
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&& (((y_width - i) & ~(1 << k)) < (1 << b_width)));
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if (shift_in_bulk || (cell->type.in(ID($shr), ID($shift), ID($shiftx)) && zpad_jump))
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db->add_edge(cell, ID::B, k, ID::Y, i, -1);
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} else {
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if (i < a_width)
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db->add_edge(cell, ID::B, k, ID::Y, i, -1);
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}
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// bidirectional shifts (positive B shifts right, negative left)
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} else if (cell->type.in(ID($shift), ID($shiftx)) && is_b_signed) {
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if (is_signed) {
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if (k != b_width - 1) {
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bool r_shift_in_bulk = i < a_width - 1;
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// assuming B is positive, can we jump into the upper zero-padding by toggling B[k]?
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bool r_zpad_jump = (((y_width - i) & ((1 << (k + 1)) - 1)) != 0 \
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&& (((y_width - i) & ~(1 << k)) <= b_high));
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// assuming B is negative, can we influence Y[i] by toggling B[k]?
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bool l = a_width - 2 - i >= b_low;
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if (a_width == 1) {
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// in case of a_width==1 we go into more detailed reasoning
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l = l && (~(i - a_width) & ((1 << (k + 1)) - 1)) != 0;
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}
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if (r_shift_in_bulk || r_zpad_jump || l)
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db->add_edge(cell, ID::B, k, ID::Y, i, -1);
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} else {
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if (y_width - i <= b_high || a_width - 2 - i >= b_low)
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db->add_edge(cell, ID::B, k, ID::Y, i, -1);
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}
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} else {
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if (a_width - 1 - i >= b_low)
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db->add_edge(cell, ID::B, k, ID::Y, i, -1);
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}
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} else {
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log_assert(false && "unreachable");
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}
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}
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}
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}
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void packed_mem_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
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{
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log_assert(cell->type == ID($mem_v2));
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Const rd_clk_enable = cell->getParam(ID::RD_CLK_ENABLE);
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int n_rd_ports = cell->getParam(ID::RD_PORTS).as_int();
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int abits = cell->getParam(ID::ABITS).as_int();
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int width = cell->getParam(ID::WIDTH).as_int();
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for (int i = 0; i < n_rd_ports; i++) {
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if (rd_clk_enable[i] != State::S0) {
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for (int k = 0; k < width; k++)
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db->add_edge(cell, ID::RD_ARST, i, ID::RD_DATA, i * width + k, -1);
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continue;
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}
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for (int j = 0; j < abits; j++)
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for (int k = 0; k < width; k++)
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db->add_edge(cell, ID::RD_ADDR, i * abits + j,
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ID::RD_DATA, i * width + k, -1);
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}
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}
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void memrd_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
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{
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log_assert(cell->type.in(ID($memrd), ID($memrd_v2)));
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int abits = cell->getParam(ID::ABITS).as_int();
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int width = cell->getParam(ID::WIDTH).as_int();
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if (cell->getParam(ID::CLK_ENABLE).as_bool()) {
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if (cell->type == ID($memrd_v2)) {
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for (int k = 0; k < width; k++)
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db->add_edge(cell, ID::ARST, 0, ID::DATA, k, -1);
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}
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return;
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}
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for (int j = 0; j < abits; j++)
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for (int k = 0; k < width; k++)
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db->add_edge(cell, ID::ADDR, j, ID::DATA, k, -1);
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}
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void mem_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
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{
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if (cell->type == ID($mem_v2))
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packed_mem_op(db, cell);
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else if (cell->type.in(ID($memrd), ID($memrd_v2)))
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memrd_op(db, cell);
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else if (cell->type.in(ID($memwr), ID($memwr_v2), ID($meminit)))
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return; /* no edges here */
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else
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log_abort();
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}
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void ff_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
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{
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int width = cell->getPort(ID::Q).size();
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if (cell->type.in(ID($dlatch), ID($adlatch), ID($dlatchsr))) {
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for (int k = 0; k < width; k++) {
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db->add_edge(cell, ID::D, k, ID::Q, k, -1);
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db->add_edge(cell, ID::EN, 0, ID::Q, k, -1);
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}
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}
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if (cell->hasPort(ID::CLR))
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for (int k = 0; k < width; k++)
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db->add_edge(cell, ID::CLR, 0, ID::Q, k, -1);
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if (cell->hasPort(ID::SET))
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for (int k = 0; k < width; k++)
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db->add_edge(cell, ID::SET, 0, ID::Q, k, -1);
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if (cell->hasPort(ID::ALOAD))
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for (int k = 0; k < width; k++)
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db->add_edge(cell, ID::ALOAD, 0, ID::Q, k, -1);
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if (cell->hasPort(ID::AD))
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for (int k = 0; k < width; k++)
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db->add_edge(cell, ID::AD, k, ID::Q, k, -1);
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if (cell->hasPort(ID::ARST))
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for (int k = 0; k < width; k++)
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db->add_edge(cell, ID::ARST, 0, ID::Q, k, -1);
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}
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PRIVATE_NAMESPACE_END
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bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL::Cell *cell)
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{
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if (cell->type.in(ID($not), ID($pos), ID($buf))) {
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bitwise_unary_op(this, cell);
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return true;
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}
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if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) {
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bitwise_binary_op(this, cell);
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return true;
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}
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if (cell->type == ID($neg)) {
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arith_neg_op(this, cell);
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return true;
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}
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if (cell->type.in(ID($add), ID($sub))) {
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arith_binary_op(this, cell);
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return true;
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}
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if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool), ID($logic_not))) {
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reduce_op(this, cell);
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return true;
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}
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if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx))) {
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shift_op(this, cell);
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return true;
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}
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if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt))) {
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compare_op(this, cell);
|
|
return true;
|
|
}
|
|
|
|
if (cell->type.in(ID($mux), ID($pmux))) {
|
|
mux_op(this, cell);
|
|
return true;
|
|
}
|
|
|
|
if (cell->type == ID($bmux)) {
|
|
bmux_op(this, cell);
|
|
return true;
|
|
}
|
|
|
|
if (cell->type == ID($demux)) {
|
|
demux_op(this, cell);
|
|
return true;
|
|
}
|
|
|
|
if (cell->type.in(ID($mem_v2), ID($memrd), ID($memrd_v2), ID($memwr), ID($memwr_v2), ID($meminit))) {
|
|
mem_op(this, cell);
|
|
return true;
|
|
}
|
|
|
|
if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
|
|
ff_op(this, cell);
|
|
return true;
|
|
}
|
|
|
|
// FIXME: $mul $div $mod $divfloor $modfloor $slice $concat
|
|
// FIXME: $lut $sop $alu $lcu $macc $fa
|
|
// FIXME: $mul $div $mod $divfloor $modfloor $pow $slice $concat $bweqx
|
|
// FIXME: $lut $sop $alu $lcu $macc $fa $logic_and $logic_or $bwmux
|
|
|
|
// FIXME: $_BUF_ $_NOT_ $_AND_ $_NAND_ $_OR_ $_NOR_ $_XOR_ $_XNOR_ $_ANDNOT_ $_ORNOT_
|
|
// FIXME: $_MUX_ $_NMUX_ $_MUX4_ $_MUX8_ $_MUX16_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
|
|
|
|
// FIXME: $specify2 $specify3 $specrule ???
|
|
// FIXME: $equiv $set_tag $get_tag $overwrite_tag $original_tag
|
|
|
|
if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover), ID($initstate), ID($anyconst), ID($anyseq), ID($allconst), ID($allseq)))
|
|
return true; // no-op: these have either no inputs or no outputs
|
|
|
|
return false;
|
|
}
|
|
|