This website requires JavaScript.
Explore
Help
Sign In
riscv
/
yosys
mirror of
https://github.com/YosysHQ/yosys.git
Watch
1
Star
0
Fork
You've already forked yosys
0
Code
Issues
Projects
Releases
Wiki
Activity
1cac671c70
yosys
/
tests
/
errors
/
syntax_err03.v
8 lines
55 B
Verilog
Raw
Blame
History
module
a
;
task
to
(
input
[
3
]
x
)
;
endtask
endmodule
Reference in New Issue
View Git Blame
Copy Permalink