Eddie Hung 8474c5b366 Merge pull request #1359 from YosysHQ/xc7dsp ... DSP inference for Xilinx (improved for ice40, initial support for ecp5)		2019-09-29 11:26:22 -07:00
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aiger	Merge pull request #1359 from YosysHQ/xc7dsp	2019-09-29 11:26:22 -07:00
blif	RTLIL::S{0,1} -> State::S{0,1}	2019-08-07 11:12:38 -07:00
btor	Corrects btor2 backend	2019-09-27 12:40:17 -04:00
edif	Add "whitebox" attribute, add "read_verilog -wb"	2019-04-18 17:45:47 +02:00
firrtl	Merge pull request #1258 from YosysHQ/eddie/cleanup	2019-08-10 09:52:14 +02:00
ilang	RTLIL::S{0,1} -> State::S{0,1}	2019-08-07 11:12:38 -07:00
intersynth	substr() -> compare()	2019-08-07 12:20:08 -07:00
json	Implement improved JSON attr/param encoding	2019-08-01 12:34:52 +02:00
protobuf	Add aiger and protobuf backends binary support	2019-09-28 09:51:48 +02:00
simplec	Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs	2019-08-06 04:47:55 +02:00
smt2	backends: smt2: use $(CXX) variable for compiler	2019-09-08 15:47:09 +08:00
smv	substr() -> compare()	2019-08-07 12:20:08 -07:00
spice	Add "whitebox" attribute, add "read_verilog -wb"	2019-04-18 17:45:47 +02:00
table	Add "whitebox" attribute, add "read_verilog -wb"	2019-04-18 17:45:47 +02:00
verilog	substr() -> compare()	2019-08-07 12:20:08 -07:00