riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
yosys/tests/arch
History
Miodrag Milanovic 0c7ac36dcf Add workflows and CODEOWNERS and fixed gitignore 2024-04-11 14:56:00 +02:00
..
anlogic Update tests 2023-06-09 14:41:45 +02:00
common Adding double_sync_ram_tdp to blockram.v 2023-12-04 15:52:03 +01:00
ecp5 ice40, ecp5, gowin: enable ABC9 by default 2023-11-13 15:28:13 +00:00
efinix efinix: Use `memory_libmap` pass. 2022-05-18 17:32:56 +02:00
fabulous fabulous: Add support for mapping carry chains 2023-02-27 09:50:34 +01:00
gatemate Update tests 2023-06-09 14:41:45 +02:00
gowin ice40, ecp5, gowin: enable ABC9 by default 2023-11-13 15:28:13 +00:00
ice40 ice40, ecp5, gowin: enable ABC9 by default 2023-11-13 15:28:13 +00:00
intel_alm Update tests 2023-06-09 14:41:45 +02:00
machxo2 put back previous test state, due to default change 2023-08-29 10:21:58 +02:00
nexus Update tests 2023-06-09 14:41:45 +02:00
quicklogic Add workflows and CODEOWNERS and fixed gitignore 2024-04-11 14:56:00 +02:00
xilinx tests: Run async2sync before sat and/or sim to handle $check cells 2024-02-01 16:14:11 +01:00
run-test.sh Enable SV for localparam use by Efinix cell_sim 2024-04-08 12:45:43 +02:00