yosys/passes
Jannis Harder 1c667fab2b
Merge pull request #3672 from jix/yw-cosim-hierarchy-fixes
sim: For yw cosim, drive parent module's signals for input ports
2023-02-15 13:45:00 +01:00
..
cmds Merge pull request #2995 from georgerennie/cover_precond 2023-02-14 17:46:31 +01:00
equiv Merge pull request #3126 from georgerennie/equiv_make_assertions 2023-02-14 17:15:55 +01:00
fsm add option to fsm_detect to ignore self-resetting 2023-01-30 16:12:53 +01:00
hierarchy Small bugfix in uniquify pass 2022-12-21 10:41:48 +01:00
memory Fitting help messages to 80 character width 2022-08-24 10:40:57 +12:00
opt Fixes for some of clang scan-build detected issues 2023-01-17 12:58:08 +01:00
pmgen Fitting help messages to 80 character width 2022-08-24 10:40:57 +12:00
proc Fixes for some of clang scan-build detected issues 2023-01-17 12:58:08 +01:00
sat sim: For yw cosim, drive parent module's signals for input ports 2023-02-13 12:26:06 +01:00
techmap Updated changelog 2023-02-08 10:11:47 +01:00
tests Add $bmux and $demux cells. 2022-01-28 23:34:41 +01:00