mirror of https://github.com/YosysHQ/yosys.git
21 lines
305 B
Plaintext
21 lines
305 B
Plaintext
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# This is a very simplified description of the capabilities of
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# the Xilinx RAMB36 core. But it is a start..
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#
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bram XILINX_RAMB36_SDP32
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init 1
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abits 10
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dbits 32
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groups 2
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ports 1 1
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wrmode 1 0
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enable 4 0
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transp 0 2
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clocks 1 2
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endbram
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match XILINX_RAMB36_SDP32
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min bits 1024
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endmatch
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