yosys/backends
Clifford Wolf 1b49380f6b Improve BTOR2 handling of undriven wires
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-26 17:42:00 +02:00
..
aiger Fix gcc invalidation behaviour for write_aiger 2019-06-20 21:56:47 -07:00
blif Fix handling of offset and upto module ports in write_blif, fixes #1040 2019-05-25 17:45:14 +02:00
btor Improve BTOR2 handling of undriven wires 2019-06-26 17:42:00 +02:00
edif Add "whitebox" attribute, add "read_verilog -wb" 2019-04-18 17:45:47 +02:00
firrtl Fix static shift operands, neg result type, minor formatting 2019-05-21 13:04:56 -07:00
ilang Support filename rewrite in backends 2019-06-18 14:39:52 -07:00
intersynth Add "whitebox" attribute, add "read_verilog -wb" 2019-04-18 17:45:47 +02:00
json Fix json formatting 2019-06-21 20:01:40 +02:00
protobuf Support filename rewrite in backends 2019-06-18 14:39:52 -07:00
simplec Fix typographical and grammatical errors and inconsistencies. 2019-01-02 13:12:17 +00:00
smt2 Escape scope names starting with dollar sign in smtio.py 2019-06-26 10:58:39 +02:00
smv Add "whitebox" attribute, add "read_verilog -wb" 2019-04-18 17:45:47 +02:00
spice Add "whitebox" attribute, add "read_verilog -wb" 2019-04-18 17:45:47 +02:00
table Add "whitebox" attribute, add "read_verilog -wb" 2019-04-18 17:45:47 +02:00
verilog Fix handling of partial init attributes in write_verilog, fixes #997 2019-05-07 19:55:36 +02:00