mirror of https://github.com/YosysHQ/yosys.git
70 lines
1.6 KiB
Plaintext
70 lines
1.6 KiB
Plaintext
# ISC License
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#
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# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
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#
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# Permission to use, copy, modify, and/or distribute this software for any
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# purpose with or without fee is hereby granted, provided that the above
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# copyright notice and this permission notice appear in all copies.
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#
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# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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# asynchronous read
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ram block $__uSRAM_AR_ {
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#(LSRAM cost)/3
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cost 43;
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# INIT supported
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init any;
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abits 6;
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widths 12 per_port;
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# single write enable wire
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port sw "W" {
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clock posedge;
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# collision not supported, but write takes precedence and read data is invalid while writing to
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# the same address
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wrtrans all new;
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optional;
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}
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port ar "R" {
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optional;
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}
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}
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# synchronous read
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# NOTE: synchronous read can be realized by the address pipeline register or data pipeline register.
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# This assumes address is synchronized
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ram block $__uSRAM_SR_ {
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cost 42;
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init any;
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abits 6;
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widths 12 per_port;
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port sw "W" {
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clock posedge;
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# collision not supported
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wrtrans all new;
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optional;
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}
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port sr "R" {
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clock posedge;
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rden;
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rdinit none;
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optional;
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}
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}
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