yosys/frontends/verilog
Clifford Wolf 7751c491fb Improved some warning messages 2014-12-27 03:40:27 +01:00
..
.gitignore Updated .gitignore file for ilang and verilog frontends 2014-10-15 01:14:38 +02:00
Makefile.inc Updated lexers & parsers to include prefixes 2014-10-15 00:48:19 +02:00
const2ast.cc Fixed two minor bugs in constant parsing 2014-11-24 14:39:24 +01:00
preproc.cc Re-introduced Yosys::readsome() helper function 2014-10-23 10:58:36 +02:00
verilog_frontend.cc Print "SystemVerilog" in "read_verilog -sv" log messages 2014-10-16 10:31:54 +02:00
verilog_frontend.h Added warning for use of 'z' constants in HDL 2014-11-14 19:59:50 +01:00
verilog_lexer.l Improved some warning messages 2014-12-27 03:40:27 +01:00
verilog_parser.y Fixed supply0/supply1 with many wires 2014-12-11 13:56:20 +01:00