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Xiretza 17163cf43a Add flooring modulo operator The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $modfloor cell provides this flooring modulo (also known as "remainder" in several languages, but this name is ambiguous). This commit also fixes the handling of $mod in opt_expr, which was previously optimized as if it was $modfloor.	2020-05-28 22:59:03 +02:00
..
Makefile.inc	initial import	2013-01-05 11:13:26 +01:00
verilog_backend.cc	Add flooring modulo operator	2020-05-28 22:59:03 +02:00

The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $modfloor cell provides this flooring modulo (also known as "remainder"
in several languages, but this name is ambiguous).

This commit also fixes the handling of $mod in opt_expr, which was
previously optimized as if it was $modfloor.

2020-05-28 22:59:03 +02:00

Makefile.inc

initial import

2013-01-05 11:13:26 +01:00

verilog_backend.cc

Add flooring modulo operator

2020-05-28 22:59:03 +02:00