mirror of https://github.com/YosysHQ/yosys.git
521 lines
15 KiB
C++
521 lines
15 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2020 R. Ou <rqou@robertou.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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RTLIL::Wire *makexorbuffer(RTLIL::Module *module, SigBit inwire, const char *cellname)
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{
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RTLIL::Wire *outwire = nullptr;
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if (inwire == SigBit(true))
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{
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// Constant 1
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outwire = module->addWire(
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module->uniquify(stringf("$xc2fix$%s_BUF1_XOR_OUT", cellname)));
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auto xor_cell = module->addCell(
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module->uniquify(stringf("$xc2fix$%s_BUF1_XOR", cellname)),
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"\\MACROCELL_XOR");
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xor_cell->setParam("\\INVERT_OUT", true);
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xor_cell->setPort("\\OUT", outwire);
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}
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else if (inwire == SigBit(false))
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{
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// Constant 0
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outwire = module->addWire(
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module->uniquify(stringf("$xc2fix$%s_BUF0_XOR_OUT", cellname)));
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auto xor_cell = module->addCell(
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module->uniquify(stringf("$xc2fix$%s_BUF0_XOR", cellname)),
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"\\MACROCELL_XOR");
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xor_cell->setParam("\\INVERT_OUT", false);
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xor_cell->setPort("\\OUT", outwire);
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}
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else if (inwire == SigBit(RTLIL::State::Sx))
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{
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// x; treat as 0
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log_warning("While buffering, changing x to 0 into cell %s\n", cellname);
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outwire = module->addWire(
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module->uniquify(stringf("$xc2fix$%s_BUF0_XOR_OUT", cellname)));
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auto xor_cell = module->addCell(
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module->uniquify(stringf("$xc2fix$%s_BUF0_XOR", cellname)),
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"\\MACROCELL_XOR");
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xor_cell->setParam("\\INVERT_OUT", false);
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xor_cell->setPort("\\OUT", outwire);
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}
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else
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{
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auto inwire_name = inwire.wire->name.c_str();
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outwire = module->addWire(
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module->uniquify(stringf("$xc2fix$%s_BUF_XOR_OUT", inwire_name)));
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auto and_to_xor_wire = module->addWire(
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module->uniquify(stringf("$xc2fix$%s_BUF_AND_OUT", inwire_name)));
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auto and_cell = module->addCell(
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module->uniquify(stringf("$xc2fix$%s_BUF_AND", inwire_name)),
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"\\ANDTERM");
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and_cell->setParam("\\TRUE_INP", 1);
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and_cell->setParam("\\COMP_INP", 0);
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and_cell->setPort("\\OUT", and_to_xor_wire);
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and_cell->setPort("\\IN", inwire);
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and_cell->setPort("\\IN_B", SigSpec());
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auto xor_cell = module->addCell(
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module->uniquify(stringf("$xc2fix$%s_BUF_XOR", inwire_name)),
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"\\MACROCELL_XOR");
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xor_cell->setParam("\\INVERT_OUT", false);
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xor_cell->setPort("\\IN_PTC", and_to_xor_wire);
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xor_cell->setPort("\\OUT", outwire);
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}
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return outwire;
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}
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RTLIL::Wire *makeptermbuffer(RTLIL::Module *module, SigBit inwire)
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{
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auto inwire_name = inwire.wire->name.c_str();
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auto outwire = module->addWire(
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module->uniquify(stringf("$xc2fix$%s_BUF_AND_OUT", inwire_name)));
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auto and_cell = module->addCell(
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module->uniquify(stringf("$xc2fix$%s_BUF_AND", inwire_name)),
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"\\ANDTERM");
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and_cell->setParam("\\TRUE_INP", 1);
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and_cell->setParam("\\COMP_INP", 0);
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and_cell->setPort("\\OUT", outwire);
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and_cell->setPort("\\IN", inwire);
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and_cell->setPort("\\IN_B", SigSpec());
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return outwire;
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}
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struct Coolrunner2FixupPass : public Pass {
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Coolrunner2FixupPass() : Pass("coolrunner2_fixup", "insert necessary buffer cells for CoolRunner-II architecture") { }
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void help() YS_OVERRIDE
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{
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log("\n");
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log(" coolrunner2_fixup [options] [selection]\n");
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log("\n");
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log("Insert necessary buffer cells for CoolRunner-II architecture.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing COOLRUNNER2_FIXUP pass (insert necessary buffer cells for CoolRunner-II architecture).\n");
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extra_args(args, 1, design);
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for (auto module : design->selected_modules())
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{
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SigMap sigmap(module);
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// Find all the FF outputs
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pool<SigBit> sig_fed_by_ff;
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for (auto cell : module->selected_cells())
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{
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if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N",
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"\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE"))
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{
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auto output = sigmap(cell->getPort("\\Q")[0]);
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sig_fed_by_ff.insert(output);
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}
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}
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// Find all the XOR outputs
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pool<SigBit> sig_fed_by_xor;
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for (auto cell : module->selected_cells())
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{
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if (cell->type == "\\MACROCELL_XOR")
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{
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auto output = sigmap(cell->getPort("\\OUT")[0]);
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sig_fed_by_xor.insert(output);
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}
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}
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// Find all the input/inout outputs
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pool<SigBit> sig_fed_by_io;
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for (auto cell : module->selected_cells())
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{
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if (cell->type.in("\\IBUF", "\\IOBUFE"))
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{
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if (cell->hasPort("\\O")) {
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auto output = sigmap(cell->getPort("\\O")[0]);
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sig_fed_by_io.insert(output);
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}
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}
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}
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// Find all the pterm outputs
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pool<SigBit> sig_fed_by_pterm;
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for (auto cell : module->selected_cells())
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{
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if (cell->type == "\\ANDTERM")
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{
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auto output = sigmap(cell->getPort("\\OUT")[0]);
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sig_fed_by_pterm.insert(output);
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}
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}
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// Find all the bufg outputs
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pool<SigBit> sig_fed_by_bufg;
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for (auto cell : module->selected_cells())
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{
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if (cell->type == "\\BUFG")
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{
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auto output = sigmap(cell->getPort("\\O")[0]);
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sig_fed_by_bufg.insert(output);
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}
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}
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// Find all the bufgsr outputs
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pool<SigBit> sig_fed_by_bufgsr;
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for (auto cell : module->selected_cells())
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{
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if (cell->type == "\\BUFGSR")
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{
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auto output = sigmap(cell->getPort("\\O")[0]);
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sig_fed_by_bufgsr.insert(output);
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}
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}
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// Find all the bufgts outputs
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pool<SigBit> sig_fed_by_bufgts;
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for (auto cell : module->selected_cells())
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{
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if (cell->type == "\\BUFGTS")
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{
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auto output = sigmap(cell->getPort("\\O")[0]);
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sig_fed_by_bufgts.insert(output);
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}
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}
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// This is used to fix the input -> FF -> output scenario
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pool<SigBit> sig_fed_by_ibuf;
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for (auto cell : module->selected_cells())
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{
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if (cell->type == "\\IBUF")
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{
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auto output = sigmap(cell->getPort("\\O")[0]);
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sig_fed_by_ibuf.insert(output);
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}
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}
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// Find all of the sinks for each output from an IBUF
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dict<SigBit, std::pair<int, RTLIL::Cell *>> ibuf_fanouts;
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for (auto cell : module->selected_cells())
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{
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for (auto &conn : cell->connections())
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{
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if (cell->input(conn.first))
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{
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for (auto wire_in : sigmap(conn.second))
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{
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if (sig_fed_by_ibuf[wire_in])
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{
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auto existing_count = ibuf_fanouts[wire_in].first;
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ibuf_fanouts[wire_in] =
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std::pair<int, RTLIL::Cell *>(existing_count + 1, cell);
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}
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}
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}
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}
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}
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dict<SigBit, RTLIL::Cell *> ibuf_out_to_packed_reg_cell;
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pool<SigBit> packed_reg_out;
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for (auto x : ibuf_fanouts)
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{
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auto ibuf_out_wire = x.first;
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auto fanout_count = x.second.first;
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auto maybe_ff_cell = x.second.second;
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// The register can be packed with the IBUF only if it's
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// actually a register and it's the only fanout. Otherwise,
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// the pad-to-zia path has to be used up and the register
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// can't be packed with the ibuf.
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if (fanout_count == 1 && maybe_ff_cell->type.in(
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"\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N",
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"\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE"))
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{
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SigBit input;
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if (maybe_ff_cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP"))
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input = sigmap(maybe_ff_cell->getPort("\\T")[0]);
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else
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input = sigmap(maybe_ff_cell->getPort("\\D")[0]);
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SigBit output = sigmap(maybe_ff_cell->getPort("\\Q")[0]);
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if (input == ibuf_out_wire)
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{
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log("Found IBUF %s that can be packed with FF %s (type %s)\n",
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ibuf_out_wire.wire->name.c_str(),
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maybe_ff_cell->name.c_str(),
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maybe_ff_cell->type.c_str());
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ibuf_out_to_packed_reg_cell[ibuf_out_wire] = maybe_ff_cell;
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packed_reg_out.insert(output);
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}
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}
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}
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for (auto cell : module->selected_cells())
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{
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if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N",
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"\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE"))
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{
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// Buffering FF inputs. FF inputs can only come from either
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// an IO pin or from an XOR. Otherwise AND/XOR cells need
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// to be inserted.
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SigBit input;
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if (cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP"))
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input = sigmap(cell->getPort("\\T")[0]);
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else
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input = sigmap(cell->getPort("\\D")[0]);
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// If the input wasn't an XOR nor an IO, then a buffer
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// definitely needs to be added.
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// Otherwise, if it is an IO, only leave unbuffered
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// if we're being packed with the IO.
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if ((!sig_fed_by_xor[input] && !sig_fed_by_io[input]) ||
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(sig_fed_by_io[input] && ibuf_out_to_packed_reg_cell[input] != cell))
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{
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log("Buffering input to \"%s\"\n", cell->name.c_str());
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auto xor_to_ff_wire = makexorbuffer(module, input, cell->name.c_str());
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if (cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP"))
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cell->setPort("\\T", xor_to_ff_wire);
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else
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cell->setPort("\\D", xor_to_ff_wire);
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}
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// Buffering FF clocks. FF clocks can only come from either
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// a pterm or a bufg. In some cases this will be handled
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// in coolrunner2_sop (e.g. if clock is generated from
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// AND-ing two signals) but not in all cases.
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SigBit clock;
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if (cell->type.in("\\LDCP", "\\LDCP_N"))
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clock = sigmap(cell->getPort("\\G")[0]);
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else
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clock = sigmap(cell->getPort("\\C")[0]);
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if (!sig_fed_by_pterm[clock] && !sig_fed_by_bufg[clock])
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{
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log("Buffering clock to \"%s\"\n", cell->name.c_str());
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auto pterm_to_ff_wire = makeptermbuffer(module, clock);
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if (cell->type.in("\\LDCP", "\\LDCP_N"))
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cell->setPort("\\G", pterm_to_ff_wire);
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else
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cell->setPort("\\C", pterm_to_ff_wire);
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}
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// Buffering FF set/reset. This can only come from either
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// a pterm or a bufgsr.
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SigBit set;
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set = sigmap(cell->getPort("\\PRE")[0]);
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if (set != SigBit(false))
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{
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if (!sig_fed_by_pterm[set] && !sig_fed_by_bufgsr[set])
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{
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log("Buffering set to \"%s\"\n", cell->name.c_str());
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auto pterm_to_ff_wire = makeptermbuffer(module, set);
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cell->setPort("\\PRE", pterm_to_ff_wire);
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}
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}
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SigBit reset;
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reset = sigmap(cell->getPort("\\CLR")[0]);
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if (reset != SigBit(false))
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{
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if (!sig_fed_by_pterm[reset] && !sig_fed_by_bufgsr[reset])
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{
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log("Buffering reset to \"%s\"\n", cell->name.c_str());
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auto pterm_to_ff_wire = makeptermbuffer(module, reset);
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cell->setPort("\\CLR", pterm_to_ff_wire);
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}
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}
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// Buffering FF clock enable
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// FIXME: This doesn't fully fix PTC conflicts
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// FIXME: Need to ensure constant enables are optimized out
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if (cell->type.in("\\FDCPE", "\\FDCPE_N", "\\FDDCPE"))
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{
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SigBit ce;
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ce = sigmap(cell->getPort("\\CE")[0]);
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if (!sig_fed_by_pterm[ce])
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{
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log("Buffering clock enable to \"%s\"\n", cell->name.c_str());
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auto pterm_to_ff_wire = makeptermbuffer(module, ce);
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cell->setPort("\\CE", pterm_to_ff_wire);
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}
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}
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}
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}
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for (auto cell : module->selected_cells())
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{
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if (cell->type == "\\IOBUFE")
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{
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// Buffer IOBUFE inputs. This can only be fed from an XOR or FF.
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SigBit input = sigmap(cell->getPort("\\I")[0]);
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if ((!sig_fed_by_xor[input] && !sig_fed_by_ff[input]) ||
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packed_reg_out[input])
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{
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log("Buffering input to \"%s\"\n", cell->name.c_str());
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auto xor_to_io_wire = makexorbuffer(module, input, cell->name.c_str());
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cell->setPort("\\I", xor_to_io_wire);
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}
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// Buffer IOBUFE enables. This can only be fed from a pterm
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// or a bufgts.
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if (cell->hasPort("\\E"))
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{
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SigBit oe;
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oe = sigmap(cell->getPort("\\E")[0]);
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if (!sig_fed_by_pterm[oe] && !sig_fed_by_bufgts[oe])
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{
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log("Buffering output enable to \"%s\"\n", cell->name.c_str());
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auto pterm_to_oe_wire = makeptermbuffer(module, oe);
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cell->setPort("\\E", pterm_to_oe_wire);
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}
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}
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}
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}
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// Now we have to fix up some cases where shared logic can
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// cause XORs to have multiple fanouts to something other than
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// pterms (which is not ok)
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// Find all the XOR outputs
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dict<SigBit, RTLIL::Cell *> xor_out_to_xor_cell;
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for (auto cell : module->selected_cells())
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{
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if (cell->type == "\\MACROCELL_XOR")
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{
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auto output = sigmap(cell->getPort("\\OUT")[0]);
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xor_out_to_xor_cell[output] = cell;
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}
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}
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// Find all of the sinks for each output from an XOR
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pool<SigBit> xor_fanout_once;
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for (auto cell : module->selected_cells())
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{
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if (cell->type == "\\ANDTERM")
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continue;
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for (auto &conn : cell->connections())
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{
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if (cell->input(conn.first))
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{
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for (auto wire_in : sigmap(conn.second))
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{
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auto xor_cell = xor_out_to_xor_cell[wire_in];
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if (xor_cell)
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{
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if (xor_fanout_once[wire_in])
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{
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log("Additional fanout found for %s into %s (type %s), duplicating\n",
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xor_cell->name.c_str(),
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cell->name.c_str(),
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cell->type.c_str());
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auto new_xor_cell = module->addCell(
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module->uniquify(xor_cell->name), xor_cell);
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auto new_wire = module->addWire(
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module->uniquify(wire_in.wire->name));
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new_xor_cell->setPort("\\OUT", new_wire);
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cell->setPort(conn.first, new_wire);
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}
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xor_fanout_once.insert(wire_in);
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}
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}
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}
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}
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}
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// Do the same fanout fixing for OR terms. By doing this
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// after doing XORs, both pieces will be duplicated when necessary.
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// Find all the OR outputs
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dict<SigBit, RTLIL::Cell *> or_out_to_or_cell;
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|
for (auto cell : module->selected_cells())
|
|
{
|
|
if (cell->type == "\\ORTERM")
|
|
{
|
|
auto output = sigmap(cell->getPort("\\OUT")[0]);
|
|
or_out_to_or_cell[output] = cell;
|
|
}
|
|
}
|
|
|
|
// Find all of the sinks for each output from an OR
|
|
pool<SigBit> or_fanout_once;
|
|
for (auto cell : module->selected_cells())
|
|
{
|
|
for (auto &conn : cell->connections())
|
|
{
|
|
if (cell->input(conn.first))
|
|
{
|
|
for (auto wire_in : sigmap(conn.second))
|
|
{
|
|
auto or_cell = or_out_to_or_cell[wire_in];
|
|
if (or_cell)
|
|
{
|
|
if (or_fanout_once[wire_in])
|
|
{
|
|
log("Additional fanout found for %s into %s (type %s), duplicating\n",
|
|
or_cell->name.c_str(),
|
|
cell->name.c_str(),
|
|
cell->type.c_str());
|
|
|
|
auto new_or_cell = module->addCell(
|
|
module->uniquify(or_cell->name), or_cell);
|
|
auto new_wire = module->addWire(
|
|
module->uniquify(wire_in.wire->name));
|
|
new_or_cell->setPort("\\OUT", new_wire);
|
|
cell->setPort(conn.first, new_wire);
|
|
}
|
|
or_fanout_once.insert(wire_in);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
} Coolrunner2FixupPass;
|
|
|
|
PRIVATE_NAMESPACE_END
|