mirror of https://github.com/YosysHQ/yosys.git
376 lines
11 KiB
C++
376 lines
11 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "frontends/verilog/preproc.h"
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#include "frontends/ast/ast.h"
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YOSYS_NAMESPACE_BEGIN
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std::map<std::string, RTLIL::Design*> saved_designs;
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std::vector<RTLIL::Design*> pushed_designs;
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struct DesignPass : public Pass {
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DesignPass() : Pass("design", "save, restore and reset current design") { }
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~DesignPass() YS_OVERRIDE {
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for (auto &it : saved_designs)
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delete it.second;
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saved_designs.clear();
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for (auto &it : pushed_designs)
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delete it;
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pushed_designs.clear();
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}
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" design -reset\n");
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log("\n");
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log("Clear the current design.\n");
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log("\n");
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log("\n");
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log(" design -save <name>\n");
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log("\n");
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log("Save the current design under the given name.\n");
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log("\n");
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log("\n");
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log(" design -stash <name>\n");
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log("\n");
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log("Save the current design under the given name and then clear the current design.\n");
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log("\n");
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log("\n");
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log(" design -push\n");
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log("\n");
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log("Push the current design to the stack and then clear the current design.\n");
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log("\n");
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log("\n");
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log(" design -pop\n");
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log("\n");
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log("Reset the current design and pop the last design from the stack.\n");
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log("\n");
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log("\n");
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log(" design -load <name>\n");
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log("\n");
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log("Reset the current design and load the design previously saved under the given\n");
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log("name.\n");
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log("\n");
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log("\n");
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log(" design -copy-from <name> [-as <new_mod_name>] <selection>\n");
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log("\n");
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log("Copy modules from the specified design into the current one. The selection is\n");
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log("evaluated in the other design.\n");
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log("\n");
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log("\n");
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log(" design -copy-to <name> [-as <new_mod_name>] [selection]\n");
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log("\n");
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log("Copy modules from the current design into the specified one.\n");
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log("\n");
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log("\n");
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log(" design -import <name> [-as <new_top_name>] [selection]\n");
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log("\n");
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log("Import the specified design into the current design. The source design must\n");
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log("either have a selected top module or the selection must contain exactly one\n");
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log("module that is then used as top module for this command.\n");
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log("\n");
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log("\n");
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log(" design -reset-vlog\n");
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log("\n");
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log("The Verilog front-end remembers defined macros and top-level declarations\n");
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log("between calls to 'read_verilog'. This command resets this memory.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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bool got_mode = false;
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bool reset_mode = false;
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bool reset_vlog_mode = false;
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bool push_mode = false;
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bool pop_mode = false;
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bool import_mode = false;
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RTLIL::Design *copy_from_design = NULL, *copy_to_design = NULL;
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std::string save_name, load_name, as_name;
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std::vector<RTLIL::Module*> copy_src_modules;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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std::string arg = args[argidx];
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if (!got_mode && args[argidx] == "-reset") {
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got_mode = true;
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reset_mode = true;
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continue;
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}
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if (!got_mode && args[argidx] == "-reset-vlog") {
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got_mode = true;
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reset_vlog_mode = true;
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continue;
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}
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if (!got_mode && args[argidx] == "-push") {
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got_mode = true;
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push_mode = true;
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continue;
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}
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if (!got_mode && args[argidx] == "-pop") {
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got_mode = true;
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pop_mode = true;
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continue;
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}
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if (!got_mode && args[argidx] == "-save" && argidx+1 < args.size()) {
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got_mode = true;
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save_name = args[++argidx];
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continue;
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}
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if (!got_mode && args[argidx] == "-stash" && argidx+1 < args.size()) {
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got_mode = true;
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save_name = args[++argidx];
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reset_mode = true;
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continue;
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}
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if (!got_mode && args[argidx] == "-load" && argidx+1 < args.size()) {
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got_mode = true;
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load_name = args[++argidx];
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if (saved_designs.count(load_name) == 0)
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log_cmd_error("No saved design '%s' found!\n", load_name.c_str());
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continue;
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}
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if (!got_mode && args[argidx] == "-copy-from" && argidx+1 < args.size()) {
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got_mode = true;
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if (saved_designs.count(args[++argidx]) == 0)
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log_cmd_error("No saved design '%s' found!\n", args[argidx].c_str());
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copy_from_design = saved_designs.at(args[argidx]);
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copy_to_design = design;
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continue;
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}
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if (!got_mode && args[argidx] == "-copy-to" && argidx+1 < args.size()) {
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got_mode = true;
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if (saved_designs.count(args[++argidx]) == 0)
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saved_designs[args[argidx]] = new RTLIL::Design;
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copy_to_design = saved_designs.at(args[argidx]);
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copy_from_design = design;
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continue;
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}
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if (!got_mode && args[argidx] == "-import" && argidx+1 < args.size()) {
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got_mode = true;
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import_mode = true;
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if (saved_designs.count(args[++argidx]) == 0)
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log_cmd_error("No saved design '%s' found!\n", args[argidx].c_str());
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copy_from_design = saved_designs.at(args[argidx]);
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copy_to_design = design;
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as_name = args[argidx];
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continue;
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}
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if (copy_from_design != NULL && args[argidx] == "-as" && argidx+1 < args.size()) {
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as_name = args[++argidx];
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continue;
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}
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break;
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}
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if (copy_from_design != NULL)
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{
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if (copy_from_design != design && argidx == args.size() && !import_mode)
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cmd_error(args, argidx, "Missing selection.");
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RTLIL::Selection sel;
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if (argidx != args.size()) {
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handle_extra_select_args(this, args, argidx, args.size(), copy_from_design);
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sel = copy_from_design->selection_stack.back();
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copy_from_design->selection_stack.pop_back();
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argidx = args.size();
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}
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for (auto mod : copy_from_design->modules()) {
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if (sel.selected_whole_module(mod->name)) {
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copy_src_modules.push_back(mod);
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continue;
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}
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if (sel.selected_module(mod->name))
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log_cmd_error("Module %s is only partly selected.\n", log_id(mod->name));
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}
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if (import_mode) {
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for (auto module : copy_src_modules)
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{
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if (module->get_bool_attribute("\\top")) {
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copy_src_modules.clear();
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copy_src_modules.push_back(module);
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break;
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}
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}
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}
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}
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extra_args(args, argidx, design, false);
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if (!got_mode)
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cmd_error(args, argidx, "Missing mode argument.");
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if (pop_mode && pushed_designs.empty())
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log_cmd_error("No pushed designs.\n");
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if (import_mode)
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{
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std::string prefix = RTLIL::escape_id(as_name);
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pool<Module*> queue;
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dict<IdString, IdString> done;
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if (copy_to_design->module(prefix) != nullptr)
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copy_to_design->remove(copy_to_design->module(prefix));
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if (GetSize(copy_src_modules) != 1)
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log_cmd_error("No top module found in source design.\n");
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for (auto mod : copy_src_modules)
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{
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log("Importing %s as %s.\n", log_id(mod), log_id(prefix));
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RTLIL::Module *t = mod->clone();
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t->name = prefix;
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t->design = copy_to_design;
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t->attributes.erase("\\top");
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copy_to_design->add(t);
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queue.insert(t);
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done[mod->name] = prefix;
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}
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while (!queue.empty())
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{
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pool<Module*> old_queue;
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old_queue.swap(queue);
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for (auto mod : old_queue)
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for (auto cell : mod->cells())
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{
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Module *fmod = copy_from_design->module(cell->type);
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if (fmod == nullptr)
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continue;
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if (done.count(cell->type) == 0)
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{
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std::string trg_name = prefix + "." + (cell->type.c_str() + (*cell->type.c_str() == '\\'));
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log("Importing %s as %s.\n", log_id(fmod), log_id(trg_name));
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if (copy_to_design->module(trg_name) != nullptr)
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copy_to_design->remove(copy_to_design->module(trg_name));
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RTLIL::Module *t = fmod->clone();
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t->name = trg_name;
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t->design = copy_to_design;
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t->attributes.erase("\\top");
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copy_to_design->add(t);
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queue.insert(t);
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done[cell->type] = trg_name;
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}
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cell->type = done.at(cell->type);
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}
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}
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}
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else
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if (copy_to_design != NULL)
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{
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if (!as_name.empty() && copy_src_modules.size() > 1)
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log_cmd_error("Only one module can be selected in combination with -as.\n");
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for (auto mod : copy_src_modules)
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{
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std::string trg_name = as_name.empty() ? mod->name.str() : RTLIL::escape_id(as_name);
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if (copy_to_design->module(trg_name) != nullptr)
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copy_to_design->remove(copy_to_design->module(trg_name));
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RTLIL::Module *t = mod->clone();
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t->name = trg_name;
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t->design = copy_to_design;
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copy_to_design->add(t);
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}
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}
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if (!save_name.empty() || push_mode)
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{
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RTLIL::Design *design_copy = new RTLIL::Design;
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for (auto mod : design->modules())
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design_copy->add(mod->clone());
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design_copy->selection_stack = design->selection_stack;
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design_copy->selection_vars = design->selection_vars;
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design_copy->selected_active_module = design->selected_active_module;
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if (saved_designs.count(save_name))
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delete saved_designs.at(save_name);
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if (push_mode)
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pushed_designs.push_back(design_copy);
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else
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saved_designs[save_name] = design_copy;
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}
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if (reset_mode || !load_name.empty() || push_mode || pop_mode)
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{
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for (auto mod : design->modules())
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design->remove(mod);
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design->selection_stack.clear();
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design->selection_vars.clear();
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design->selected_active_module.clear();
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design->selection_stack.push_back(RTLIL::Selection());
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}
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if (reset_mode || reset_vlog_mode || !load_name.empty() || push_mode || pop_mode)
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{
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for (auto node : design->verilog_packages)
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delete node;
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design->verilog_packages.clear();
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for (auto node : design->verilog_globals)
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delete node;
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design->verilog_globals.clear();
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design->verilog_defines->clear();
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}
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if (!load_name.empty() || pop_mode)
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{
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RTLIL::Design *saved_design = pop_mode ? pushed_designs.back() : saved_designs.at(load_name);
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for (auto mod : saved_design->modules())
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design->add(mod->clone());
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design->selection_stack = saved_design->selection_stack;
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design->selection_vars = saved_design->selection_vars;
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design->selected_active_module = saved_design->selected_active_module;
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if (pop_mode) {
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delete saved_design;
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pushed_designs.pop_back();
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}
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}
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}
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} DesignPass;
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YOSYS_NAMESPACE_END
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