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15ff4cc63b
yosys
/
tests
/
hana
/
test_simulation_always_15_t...
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module
test
(
input
[
1
:
0
]
in
,
output
reg
[
1
:
0
]
out
)
;
always
@
(
in
)
out
=
in
;
endmodule
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