mirror of https://github.com/YosysHQ/yosys.git
35 lines
530 B
Verilog
35 lines
530 B
Verilog
module testbench;
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reg en;
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initial begin
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// $dumpfile("testbench.vcd");
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// $dumpvars(0, testbench);
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#5 en = 0;
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repeat (10000) begin
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#5 en = 1;
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#5 en = 0;
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end
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$display("OKAY");
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end
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reg dinA = 0;
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wire doutB;
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top uut (
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.en (en ),
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.a (dinA ),
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.b (doutB )
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);
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always @(posedge en) begin
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#3;
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dinA <= !dinA;
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end
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assert_tri b_test(.en(en), .A(dinA), .B(doutB));
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endmodule
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