mirror of https://github.com/YosysHQ/yosys.git
44 lines
830 B
Verilog
44 lines
830 B
Verilog
module testbench;
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reg clk;
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initial begin
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// $dumpfile("testbench.vcd");
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// $dumpvars(0, testbench);
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#5 clk = 0;
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repeat (10000) begin
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#5 clk = 1;
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#5 clk = 0;
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end
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$display("OKAY");
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end
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reg [15:0] D = 1;
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reg [3:0] S = 0;
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wire M2,M4,M8,M16;
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top uut (
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.S (S ),
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.D (D ),
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.M2 (M2 ),
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.M4 (M4 ),
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.M8 (M8 ),
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.M16 (M16 )
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);
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always @(posedge clk) begin
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//#3;
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D <= {D[14:0],D[15]};
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//D <= D <<< 1;
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S <= S + 1;
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end
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assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
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assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
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assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
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assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
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endmodule
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