mirror of https://github.com/YosysHQ/yosys.git
48 lines
829 B
Verilog
48 lines
829 B
Verilog
module testbench;
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reg [7:0] in;
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wire [3:0] outA,outB;
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wire [3:0] poutA,poutB;
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initial begin
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// $dumpfile("testbench.vcd");
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// $dumpvars(0, testbench);
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#5 in = 0;
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repeat (10000) begin
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#5 in = in + 1;
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end
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$display("OKAY");
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end
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top uut (
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.x(in[3:0]),
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.y(in[7:4]),
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.A(outA),
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.B(outB)
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);
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assign poutA = in[3:0] + in[7:4];
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assign poutB = in[3:0] - in[7:4];
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check_comb add_test(outA, poutA);
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check_comb sub_test(outB, poutB);
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assert_comb sub0_test(outB[2], poutB[2]);
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endmodule
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module check_comb(input [3:0] test, input [3:0] pat);
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always @*
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begin
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#1;
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if (test != pat)
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begin
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$display("ERROR: ASSERTION FAILED in %m:",$time," ",test," ",pat);
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$stop;
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end
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end
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endmodule
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