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riscv
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yosys
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https://github.com/YosysHQ/yosys.git
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138547f41b
yosys
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frontends
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Clifford Wolf
e9368a1d7e
Various fixes for memories with offsets
2015-02-14 14:21:15 +01:00
..
ast
Various fixes for memories with offsets
2015-02-14 14:21:15 +01:00
ilang
Enable bison to be customized
2015-01-08 09:56:20 -02:00
liberty
namespace Yosys
2014-09-27 16:17:53 +02:00
verific
Added log_warning() API
2014-11-09 10:44:23 +01:00
verilog
Added "read_verilog -nomeminit" and "nomeminit" attribute
2015-02-14 11:21:12 +01:00
vhdl2verilog
Header changes so it will compile on VS
2014-10-17 11:41:36 +02:00