mirror of https://github.com/YosysHQ/yosys.git
17 lines
457 B
Verilog
17 lines
457 B
Verilog
//-----------------------------------------------------
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// Design Name : parity_using_bitwise
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// File Name : parity_using_bitwise.v
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// Function : Parity using bitwise xor
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// Coder : Deepak Kumar Tala
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//-----------------------------------------------------
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module parity_using_bitwise (
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data_in , // 8 bit data in
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parity_out // 1 bit parity out
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);
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output parity_out ;
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input [7:0] data_in ;
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assign parity_out = ^data_in;
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endmodule
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