mirror of https://github.com/YosysHQ/yosys.git
10 lines
312 B
Plaintext
10 lines
312 B
Plaintext
read_verilog compare.v
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hierarchy -top top
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proc
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equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 5 t:ALU
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