mirror of https://github.com/YosysHQ/yosys.git
330 lines
5.9 KiB
Verilog
330 lines
5.9 KiB
Verilog
module inpad (
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output Q,
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(* iopad_external_pin *)
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input P
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);
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specify
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(P => Q) = 0;
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endspecify
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assign Q = P;
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endmodule
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module outpad (
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(* iopad_external_pin *)
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output P,
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input A
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);
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specify
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(A => P) = 0;
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endspecify
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assign P = A;
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endmodule
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module ckpad (
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output Q,
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(* iopad_external_pin *)
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input P
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);
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specify
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(P => Q) = 0;
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endspecify
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assign Q = P;
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endmodule
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module bipad (
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input A,
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input EN,
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output Q,
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(* iopad_external_pin *)
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inout P
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);
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assign Q = P;
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assign P = EN ? A : 1'bz;
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endmodule
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module dff (
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output reg Q,
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input D,
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(* clkbuf_sink *)
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input CLK
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);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(posedge CLK) Q <= D;
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endmodule
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module dffc (
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output reg Q,
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input D,
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(* clkbuf_sink *)
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input CLK,
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(* clkbuf_sink *)
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input CLR
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);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(posedge CLK or posedge CLR)
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if (CLR) Q <= 1'b0;
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else Q <= D;
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endmodule
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module dffp (
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output reg Q,
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input D,
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(* clkbuf_sink *)
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input CLK,
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(* clkbuf_sink *)
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input PRE
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);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(posedge CLK or posedge PRE)
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if (PRE) Q <= 1'b1;
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else Q <= D;
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endmodule
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module dffpc (
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output reg Q,
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input D,
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(* clkbuf_sink *)
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input CLK,
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(* clkbuf_sink *)
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input CLR,
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(* clkbuf_sink *)
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input PRE
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);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(posedge CLK or posedge CLR or posedge PRE)
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if (CLR) Q <= 1'b0;
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else if (PRE) Q <= 1'b1;
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else Q <= D;
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endmodule
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module dffe (
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output reg Q,
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input D,
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(* clkbuf_sink *)
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input CLK,
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input EN
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);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(posedge CLK) if (EN) Q <= D;
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endmodule
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module dffec (
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output reg Q,
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input D,
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(* clkbuf_sink *)
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input CLK,
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input EN,
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(* clkbuf_sink *)
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input CLR
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);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(posedge CLK or posedge CLR)
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if (CLR) Q <= 1'b0;
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else if (EN) Q <= D;
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endmodule
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(* lib_whitebox *)
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module dffepc (
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output reg Q,
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input D,
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(* clkbuf_sink *)
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input CLK,
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input EN,
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(* clkbuf_sink *)
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input CLR,
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(* clkbuf_sink *)
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input PRE
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);
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parameter [0:0] INIT = 1'b0;
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specify
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if (EN) (posedge CLK => (Q : D)) = 1701; // QCK -> QZ
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if (CLR) (CLR => Q) = 967; // QRT -> QZ
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if (PRE) (PRE => Q) = 1252; // QST -> QZ
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$setup(D, posedge CLK, 216); // QCK -> QDS
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$setup(EN, posedge CLK, 590); // QCK -> QEN
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endspecify
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initial Q = INIT;
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always @(posedge CLK or posedge CLR or posedge PRE)
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if (CLR) Q <= 1'b0;
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else if (PRE) Q <= 1'b1;
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else if (EN) Q <= D;
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endmodule
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// FZ FS F2 (F1 TO 0)
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(* abc9_box, lib_whitebox *)
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module AND2I0 (
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output Q,
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input A, B
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);
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specify
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(A => Q) = 698; // FS -> FZ
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(B => Q) = 639; // F2 -> FZ
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endspecify
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assign Q = A ? B : 0;
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endmodule
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(* abc9_box, lib_whitebox *)
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module mux2x0 (
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output Q,
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input S, A, B
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);
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specify
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(S => Q) = 698; // FS -> FZ
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(A => Q) = 639; // F1 -> FZ
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(B => Q) = 639; // F2 -> FZ
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endspecify
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assign Q = S ? B : A;
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endmodule
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(* abc9_box, lib_whitebox *)
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module mux2x1 (
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output Q,
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input S, A, B
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);
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specify
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(S => Q) = 698; // FS -> FZ
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(A => Q) = 639; // F1 -> FZ
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(B => Q) = 639; // F2 -> FZ
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endspecify
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assign Q = S ? B : A;
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endmodule
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(* abc9_box, lib_whitebox *)
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module mux4x0 (
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output Q,
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input S0, S1, A, B, C, D
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);
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specify
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(S0 => Q) = 1251; // TAB -> TZ
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(S1 => Q) = 1406; // TSL -> TZ
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(A => Q) = 1699; // TA1 -> TZ
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(B => Q) = 1687; // TA2 -> TZ
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(C => Q) = 1669; // TB1 -> TZ
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(D => Q) = 1679; // TB2 -> TZ
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endspecify
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assign Q = S1 ? (S0 ? D : C) : (S0 ? B : A);
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endmodule
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// S0 BSL TSL
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// S1 BAB TAB
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// S2 TBS
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// A TA1
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// B TA2
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// C TB1
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// D TB2
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// E BA1
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// F BA2
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// G BB1
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// H BB2
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// Q CZ
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(* abc9_box, lib_whitebox *)
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module mux8x0 (
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output Q,
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input S0, S1, S2, A, B, C, D, E, F, G, H
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);
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specify
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(S0 => Q) = 1593; // ('TSL', 'BSL') -> CZ
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(S1 => Q) = 1437; // ('TAB', 'BAB') -> CZ
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(S2 => Q) = 995; // TBS -> CZ
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(A => Q) = 1887; // TA1 -> CZ
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(B => Q) = 1873; // TA2 -> CZ
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(C => Q) = 1856; // TB1 -> CZ
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(D => Q) = 1860; // TB2 -> CZ
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(E => Q) = 1714; // BA1 -> CZ
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(F => Q) = 1773; // BA2 -> CZ
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(G => Q) = 1749; // BB1 -> CZ
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(H => Q) = 1723; // BB2 -> CZ
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endspecify
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assign Q = S2 ? (S1 ? (S0 ? H : G) : (S0 ? F : E)) : (S1 ? (S0 ? D : C) : (S0 ? B : A));
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endmodule
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(* blackbox *)
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(* keep *)
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module qlal4s3b_cell_macro (
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input WB_CLK,
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input WBs_ACK,
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input [31:0] WBs_RD_DAT,
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output [3:0] WBs_BYTE_STB,
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output WBs_CYC,
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output WBs_WE,
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output WBs_RD,
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output WBs_STB,
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output [16:0] WBs_ADR,
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input [3:0] SDMA_Req,
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input [3:0] SDMA_Sreq,
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output [3:0] SDMA_Done,
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output [3:0] SDMA_Active,
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input [3:0] FB_msg_out,
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input [7:0] FB_Int_Clr,
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output FB_Start,
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input FB_Busy,
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output WB_RST,
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output Sys_PKfb_Rst,
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output Clk16,
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output Clk16_Rst,
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output Clk21,
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output Clk21_Rst,
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output Sys_Pclk,
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output Sys_Pclk_Rst,
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input Sys_PKfb_Clk,
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input [31:0] FB_PKfbData,
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output [31:0] WBs_WR_DAT,
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input [3:0] FB_PKfbPush,
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input FB_PKfbSOF,
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input FB_PKfbEOF,
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output [7:0] Sensor_Int,
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output FB_PKfbOverflow,
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output [23:0] TimeStamp,
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input Sys_PSel,
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input [15:0] SPIm_Paddr,
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input SPIm_PEnable,
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input SPIm_PWrite,
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input [31:0] SPIm_PWdata,
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output SPIm_PReady,
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output SPIm_PSlvErr,
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output [31:0] SPIm_Prdata,
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input [15:0] Device_ID,
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input [13:0] FBIO_In_En,
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input [13:0] FBIO_Out,
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input [13:0] FBIO_Out_En,
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output [13:0] FBIO_In,
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inout [13:0] SFBIO,
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input Device_ID_6S,
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input Device_ID_4S,
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input SPIm_PWdata_26S,
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input SPIm_PWdata_24S,
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input SPIm_PWdata_14S,
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input SPIm_PWdata_11S,
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input SPIm_PWdata_0S,
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input SPIm_Paddr_8S,
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input SPIm_Paddr_6S,
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input FB_PKfbPush_1S,
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input FB_PKfbData_31S,
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input FB_PKfbData_21S,
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input FB_PKfbData_19S,
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input FB_PKfbData_9S,
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input FB_PKfbData_6S,
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input Sys_PKfb_ClkS,
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input FB_BusyS,
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input WB_CLKS
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);
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endmodule
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