mirror of https://github.com/YosysHQ/yosys.git
221 lines
6.0 KiB
C++
221 lines
6.0 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct PrepPass : public ScriptPass
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{
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PrepPass() : ScriptPass("prep", "generic synthesis script") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" prep [options]\n");
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log("\n");
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log("This command runs a conservative RTL synthesis. A typical application for this\n");
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log("is the preparation stage of a verification flow. This command does not operate\n");
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log("on partly selected designs.\n");
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log("\n");
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log(" -top <module>\n");
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log(" use the specified module as top module (default='top')\n");
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log("\n");
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log(" -auto-top\n");
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log(" automatically determine the top of the design hierarchy\n");
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log("\n");
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log(" -flatten\n");
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log(" flatten the design before synthesis. this will pass '-auto-top' to\n");
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log(" 'hierarchy' if no top module is specified.\n");
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log("\n");
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log(" -ifx\n");
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log(" passed to 'proc'. uses verilog simulation behavior for verilog if/case\n");
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log(" undef handling. this also prevents 'wreduce' from being run.\n");
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log("\n");
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log(" -memx\n");
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log(" simulate verilog simulation behavior for out-of-bounds memory accesses\n");
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log(" using the 'memory_memx' pass.\n");
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log("\n");
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log(" -nomem\n");
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log(" do not run any of the memory_* passes\n");
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log("\n");
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log(" -rdff\n");
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log(" do not pass -nordff to 'memory_dff'. This enables merging of FFs into\n");
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log(" memory read ports.\n");
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log("\n");
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log(" -nokeepdc\n");
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log(" do not call opt_* with -keepdc\n");
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log("\n");
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log(" -run <from_label>[:<to_label>]\n");
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log(" only run the commands between the labels (see below). an empty\n");
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log(" from label is synonymous to 'begin', and empty to label is\n");
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log(" synonymous to the end of the command list.\n");
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log("\n");
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log("\n");
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log("The following commands are executed by this synthesis command:\n");
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help_script();
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log("\n");
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}
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string top_module, fsm_opts;
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bool autotop, flatten, ifxmode, memxmode, nomemmode, nokeepdc, nordff;
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void clear_flags() YS_OVERRIDE
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{
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top_module.clear();
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autotop = false;
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flatten = false;
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ifxmode = false;
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memxmode = false;
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nomemmode = false;
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nokeepdc = false;
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nordff = true;
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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string run_from, run_to;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-top" && argidx+1 < args.size()) {
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top_module = args[++argidx];
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continue;
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}
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if (args[argidx] == "-run" && argidx+1 < args.size()) {
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size_t pos = args[argidx+1].find(':');
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if (pos == std::string::npos) {
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run_from = args[++argidx];
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run_to = args[argidx];
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} else {
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run_from = args[++argidx].substr(0, pos);
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run_to = args[argidx].substr(pos+1);
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}
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continue;
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}
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if (args[argidx] == "-auto-top") {
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autotop = true;
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continue;
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}
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if (args[argidx] == "-flatten") {
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flatten = true;
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continue;
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}
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if (args[argidx] == "-ifx") {
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ifxmode = true;
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continue;
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}
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if (args[argidx] == "-memx") {
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memxmode = true;
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continue;
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}
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if (args[argidx] == "-nomem") {
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nomemmode = true;
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continue;
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}
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if (args[argidx] == "-nordff") {
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nordff = true;
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continue;
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}
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if (args[argidx] == "-rdff") {
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nordff = false;
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continue;
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}
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if (args[argidx] == "-nokeepdc") {
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nokeepdc = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (!design->full_selection())
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log_cmd_error("This comannd only operates on fully selected designs!\n");
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log_header(design, "Executing PREP pass.\n");
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log_push();
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run_script(design, run_from, run_to);
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log_pop();
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}
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void script() YS_OVERRIDE
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{
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if (check_label("begin"))
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{
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if (help_mode) {
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run("hierarchy -check [-top <top> | -auto-top]");
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} else {
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if (top_module.empty()) {
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if (flatten || autotop)
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run("hierarchy -check -auto-top");
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else
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run("hierarchy -check");
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} else
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run(stringf("hierarchy -check -top %s", top_module.c_str()));
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}
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}
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if (check_label("coarse"))
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{
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if (help_mode)
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run("proc [-ifx]");
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else
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run(ifxmode ? "proc -ifx" : "proc");
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if (help_mode || flatten)
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run("flatten", "(if -flatten)");
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run(nokeepdc ? "opt_expr" : "opt_expr -keepdc");
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run("opt_clean");
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run("check");
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run(nokeepdc ? "opt" : "opt -keepdc");
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if (!ifxmode) {
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if (help_mode)
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run("wreduce [-memx]");
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else
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run(memxmode ? "wreduce -memx" : "wreduce");
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}
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if (!nomemmode) {
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run(string("memory_dff") + (help_mode ? " [-nordff]" : nordff ? " -nordff" : ""));
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if (help_mode || memxmode)
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run("memory_memx", "(if -memx)");
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run("opt_clean");
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run("memory_collect");
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}
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run(nokeepdc ? "opt -fast" : "opt -keepdc -fast");
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}
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if (check_label("check"))
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{
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run("stat");
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run("check");
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}
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}
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} PrepPass;
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PRIVATE_NAMESPACE_END
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