mirror of https://github.com/YosysHQ/yosys.git
102 lines
1.2 KiB
Plaintext
102 lines
1.2 KiB
Plaintext
# Case 1.
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read_verilog << EOT
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module top(...);
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input clk;
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input sel;
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input [3:0] ra;
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input [3:0] wa;
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input wd;
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output [3:0] rd;
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reg [3:0] mem[0:15];
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integer i;
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initial begin
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for (i = 0; i < 16; i = i + 1)
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mem[i] <= i;
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end
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assign rd = mem[ra];
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always @(posedge clk) begin
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mem[wa] <= {4{sel ? wd : mem[wa][0]}};
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end
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endmodule
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EOT
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hierarchy -auto-top
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proc
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opt_clean
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design -save start
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memory_map
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design -save preopt
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design -load start
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opt_mem_feedback
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memory_map
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design -save postopt
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equiv_opt -assert -run prepare: :
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design -reset
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# Case 2.
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read_verilog << EOT
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module top(...);
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input clk;
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input s1;
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input s2;
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input s3;
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input [3:0] ra;
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input [3:0] wa;
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input wd;
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output rd;
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reg mem[0:15];
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integer i;
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initial begin
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for (i = 0; i < 16; i = i + 1)
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mem[i] <= ^i;
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end
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assign rd = mem[ra];
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wire ta = s1 ? wd : mem[wa];
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wire tb = s2 ? wd : ta;
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wire tc = s3 ? tb : ta;
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always @(posedge clk) begin
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mem[wa] <= tc;
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end
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endmodule
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EOT
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hierarchy -auto-top
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proc
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opt_clean
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design -save start
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memory_map
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design -save preopt
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design -load start
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opt_mem_feedback
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memory_map
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design -save postopt
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equiv_opt -assert -run prepare: :
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